WM8960 datasheet(81/92 Pages) WOLFSON

81 / 92 page

Production Data

WM8960

PD, August 2013, Rev 4.2

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

MBSEL

Microphone Bias Voltage Control

0 = 0.9 * AVDD

1 = 0.65 * AVDD

Input Signal

Path

R49 (31h)

Class D

Control (1)

Reserved

7:6

SPK_OP_EN[1:0]

Enable Class D Speaker Outputs

00 = Off

01 = Left speaker only

10 = Right speaker only

11 = Left and right speakers enabled

Enabling the

Outputs

5:0

110111

Reserved

R50 (32h)

8:0

001001101

Reserved

R51 (33h)

Class D

Control (2)

8:6

010

Reserved

5:3

DCGAIN[2:0]

000

DC Speaker Boost (Boosts speaker DC output

level by up to 1.8 x on left and right channels)

000 = 1.00x boost (+0dB)

001 = 1.27x boost (+2.1dB)

010 = 1.40x boost (+2.9dB)

011 = 1.52x boost (+3.6dB)

100 = 1.67x boost (+4.5dB)

101 = 1.8x boost (+5.1dB)

110 to 111 = Reserved

Analogue

Outputs

2:0

ACGAIN[2:0]

000

AC Speaker Boost (Boosts speaker AC output

signal by up to 1.8 x on left and right channels)

000 = 1.00x boost (+0dB)

001 = 1.27x boost (+2.1dB)

010 = 1.40x boost (+2.9dB)

011 = 1.52x boost (+3.6dB)

100 = 1.67x boost (+4.5dB)

101 = 1.8x boost (+5.1dB)

110 to 111 = Reserved

Analogue

Outputs

R52 (34h)

PLL (1)

8:6

OPCLKDIV[2:0]

000

SYSCLK Output to GPIO Clock Division ratio

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 5.5

101 = SYSCLK / 6

General

Purpose Input /

Output

SDM

Enable Integer Mode

0 = Integer mode

1 = Fractional mode

Clocking and

Sample Rates

PLLPRESCALE

Divide MCLK by 2 before input to PLL

0 = Divide by 1

1 = Divide by 2

Clocking and

Sample Rates

3:0

PLLN[3:0]

1000

Integer (N) part of PLL input/output frequency

ratio. Use values greater than 5 and less than

13.

Clocking and

Sample Rates

R53 (35h)

PLL (2)

Reserved

7:0

PLLK[23:16]

00110001

Fractional (K) part of PLL1 input/output

frequency ratio (treat as one 24-digit binary

number).

Clocking and

Sample Rates

R54 (36h)

PLL (3)

Reserved

7:0

PLLK[15:8]

00100110

Fractional (K) part of PLL1 input/output

frequency ratio (treat as one 24-digit binary

number).

Clocking and

Sample Rates

WM8960 データシート(PDF) 81 Page - Wolfson Microelectronics plc

WM8960 データシート(HTML) 81 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

データシートダウンロード

リンク URL

WM8960 データシート(PDF) 81 Page - Wolfson Microelectronics plc

WM8960 データシート(HTML) 81 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

データシート ダウンロード

リンク URL

データシートダウンロード