AN2021 datasheet(24/39 Pages) STMICROELECTRONICS

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AN2021

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Then, in the interrupt routines associated with the XPxIC, the respective flags in the

XIRxSEL registers must be cleared. Since the XIRxSEL registers are not bit addressable, a

pair of registers (a pair for each XIRxSEL) is provided to set and clear the bits of XIRxSEL

without risking to overwrite requests coming after reading the register and before writing it.

Therefore, the following registers must be written to clear the flags:

●

in the CAN1 interrupt routine, XIR0CLR (@ EB14h) = 0x0001

●

in the CAN2 interrupt routine, XIR1CLR (@ EB24h) = 0x0001

●

in the PLL unlock interrupt routine, XIR3CLR (@ EB44h) = 0x0020

Additional information on the X-Interrupt multiplexer structure

Figure 2: X-Interrupt basic structure shows that the X-Interrupt sources are connected to the

interrupt request flag of the XIRxSEL registers and to the XPxIR request flag via an AND

gate with the enable bit. This AND gate is activated by a transition on the Interrupt source

line and not by the latched value in the XIRxSEL register. This means that:

●

A transition on the IT source line generates an interrupt to the ST10 core if the source

is enabled.

●

Writing to an interrupt request flag in an XIRxSEL register does not generate an

interrupt to the ST10 core.

Example: If XIR0SEL = 0x0100: CAN1 interrupt enabled on XP0IC interrupt

To trigger by software the CAN1 interrupt routine with the XP0IC register, the following code

must be used:

XIR0SET = 0x0001;/* Set CAN1 interrupt request Flag in XIR0SEL */

XP0IC = XP0IC | 0x0080;/* Set XP0IR flag, generate an interrupt */

Executing only the first line only sets the flag in the XIR0SEL register but it is not seen by the

AND gate and cannot set the XP0IR flag.

AN2021 データシート(PDF) 24 Page - STMicroelectronics