AN2021 datasheet(27/39 Pages) STMICROELECTRONICS

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AN2021

Modified registers

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Accesses to the XPeripherals are configured through three pairs of specific XBus

configuration registers, equivalent to the External Bus register BUSCONx and ADDRSELx.

Therefore, several XPeripherals are sharing the same pair, with the consequence that

accesses to a disabled XPeripherals are only redirected to external memory if all the other

XPeripherals sharing the same pair of registers are disabled.

The XPeripherals are grouped as follows:

●

CAN1, CAN2, XASC, XSSC, XI2C, XPWM, XRTC and XMISC: Accesses to the

00’E800h-00’EFFFh range are redirected to external memory only if all corresponding

bits are cleared

●

XRAM1: Accesses to the 00’E000h-00’E7FFh range are redirected to external memory

if bit XRAM1EN is cleared

●

XRAM2: Accesses the 09’0000h-0F’FFFFh range (default value in XADRS3 register,

refer to Section 4.1: XADRS3 register) are redirected to external memory if bit

XRAM2EN is cleared

3.1.1

Hardware impact

None.

3.1.2

Software impact

None if the ST10F269 software is not writing to the reserved bit.

4RTCEN

RTC Enable Bit

0: Accesses to the on-chip Real Time Clock are disabled, external access

performed.

1: The on-chip Real Time Clock is enabled and can be accessed.

3XRAM2EN

XRAM2 Enable Bit

0: Accesses to the on-chip XRAM2 block are disabled, external access

performed.

1: The on-chip XRAM2 is enabled and can be accessed.

2XRAM1EN

XRAM1 Enable Bit

0: Accesses to the on-chip XRAM1 block are disabled, external access

performed.

1: The on-chip XRAM1 is enabled and can be accessed.

1CAN2EN

CAN2 Enable Bit

0: Accesses to the CAN2 XPeripheral and its functions are disabled (P4.4

and P4.7 pins can be used as general purpose I/Os)

1: The CAN2 XPeripheral is enabled and can be accessed.

0CAN1EN

CAN1 Enable Bit

0: Accesses to the CAN1 XPeripheral and its functions are disabled (P4.5

and P4.6 pins can be used as general purpose I/Os)

1: The CAN1 XPeripheral is enabled and can be accessed.

Table 15.

XPERCON register description (continued)

Bit

Bit name

Function

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