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ST9 データシート(PDF) 53 Page - STMicroelectronics |
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ST9 データシート(HTML) 53 Page - STMicroelectronics |
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53 / 146 page  53/146 ST9 USER GUIDE being accidentally masked even in the case of a program failure. In any case, the Top Level Interrupt uses the third fixed vector at addresses 4 and 5 in program memory. As the name im- plies, it has a fixed priority that is higher than any other interrupt request. Though it does not clear the IEN bit when acknowledged, unlike all other interrupt requests, its service routine cannot be interrupted by any cause, including the Top Level Interrupt itself. The simplified block diagram is the following: Figure 21 . Top-Level Interrupt Simplified Block Diagram NMI pin Edge trigger event selection: one bit of EIVR Watchdog/NMI source selection: One bit of CICR Pending Bit One bit of NICR Top Level Interrupt to the core Watchdog timer End of Count one bit of EIVR Top Level not maskable Interrupt bit Interrupt enable: Two bits of CICR A detailed block diagram is provided in Section 7 |
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