AR0130CSSC00SPBA0-DR datasheet(7/53 Pages) ONSEMI

7 / 53 page

AR0130 DS Rev. L Pub. 6/15 EN

©Semiconductor Components Industries, LLC, 2015.

AR0130: 1/3-Inch CMOS Digital Image Sensor

Functional Overview

provides further data path corrections and applies digital gain). The pixel data are

output at a rate of up to 74.25 Mp/s, in parallel to frame and line synchronization

signals.

Figure 2:

Typical Configuration: Parallel Pixel Data Interface

Notes:

1. All power supplies must be adequately decoupled.

2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for

slower two-wire speed.

3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.

4. ON Semiconductor recommends that VDD_SLVS pad (only available in bare die) is left unconnected.

5. ON Semiconductor recommends that 0.1μF and 10μF decoupling capacitors for each power supply

are mounted as close as possible to the pad. Actual values and results may vary depending on lay-

out and design considerations. Check the AR0130 demo headboard schematics for circuit recom-

mendations.

6. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-

pling with the digital power planes is minimized.

7. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.

VDD

Master clock

(6–50 MHz)

SDATA

SCLK

Reserved

FRAME_VALID

DOUT [11:0]

EXTCLK

DGND

Digital

ground

Analog

ground

Digital

core

power1

controller

From

Controller

LINE_VALID

PIXCLK

RESET_BAR

VDD_IO

Digital

I/O

power1

VAA

VAA_PIX

Analog

power1

VDD_PLL

PLL

power1

Analog

power1

VAA_PIX

VDD_IO

VDD_PLL

VDD

VAA

TRIGGER

OE_BAR

STANDBY

AGND

SADDR

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