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AR0130CSSC00SPBA0-DR データシート(PDF) 34 Page - ON Semiconductor

部品番号 AR0130CSSC00SPBA0-DR
部品情報  CMOS Digital Image Sensor
PDF  53 Pages
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AR0130CSSC00SPBA0-DR データシート(HTML) 34 Page - ON Semiconductor

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AR0130 DS Rev. L Pub. 6/15 EN
34
©Semiconductor Components Industries, LLC, 2015.
AR0130: 1/3-Inch CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Single READ from Random Location
This sequence (Figure 20) starts with a dummy WRITE to the 16-bit address that is to be
used for the READ. The master terminates the WRITE by generating a restart condition.
The master then sends the 8-bit read slave address/data direction byte and clocks out
one byte of register data. The master terminates the READ by generating a no-acknowl-
edge bit followed by a stop condition. Figure 20 shows how the internal register address
maintained by the AR0130 is loaded and incremented as the sequence proceeds.
Figure 20:
Single READ from Random Location
Single READ from Current Location
This sequence (Figure 21) performs a read using the current value of the AR0130 internal
register address. The master terminates the READ by generating a no-acknowledge bit
followed by a stop condition. The figure shows two independent READ sequences.
Figure 21:
Single READ from Current Location
Sequential READ, Start from Random Location
This sequence (Figure 22) starts in the same way as the single READ from random loca-
tion (Figure 20). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte READs until “L” bytes have been read.
Figure 22:
Sequential READ, Start from Random Location
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
slave to master
master to slave
Slave Address
0
S
A Reg Address[15:8]
A
Reg Address[7:0]
Slave Address
A
A
1
Sr
Read Data
P
Previous Reg Address, N
Reg Address, M
M+1
A
Slave Address
1
S
A
Read Data
Slave Address
A
1
S
P
Read Data
P
Previous Reg Address, N
Reg Address, N+1
N+2
A
A
Slave Address
0
S
Sr
A Reg Address[15:8]
Read Data
Read Data
A
Reg Address[7:0] A
Read Data
Slave Address
Previous Reg Address, N
Reg Address, M
M+1
M+2
M+1
M+3
A
1
Read Data
Read Data
M+L-2
M+L-1
M+L
A P
A
A
A
A



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