STCOM10 datasheet(14/58 Pages) STMICROELECTRONICS

14 / 58 page

Description

STCOM

14/58

DocID028515 Rev 1

1.3.4

DMA controller (DMA)

The STCOM embeds 1 general purpose dual port DMA controller with 8 channels. It is able

to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers.

It features dedicated FIFOs for APB/AHB peripherals, a supports burst transfer and is

designed to provide the maximum peripheral bandwidth (AHB/APB).

The DMA controller supports circular buffer management, so that no specific code is needed

when the controller reaches the end of the buffer. It also has a double buffering feature,

which automates the use and switching of two memory buffers without requiring any special

code.

Each channel is connected to dedicated hardware DMA requests, with support for

a software trigger on each stream. Configuration is made by software and transfer sizes

between source and destination are independent.

GPIO02

GPIO02 global interrupt

GPIO03

GPIO03 global interrupt

GPIO04

GPIO04 global interrupt

GPIO05

GPIO05 global interrupt

GPIO06

GPIO06 global interrupt

GPIO07

GPIO07 global interrupt

GPIO08

GPIO08 global interrupt

GPIO09

GPIO09 global interrupt

GPIO10

GPIO10 global interrupt

GPT4

GPT4 - global interrupt

GPT5

GPT5 - global interrupt

GPT6

GPT6 - global interrupt

GPT7

GPT7 - global interrupt

Reserved

Table 2. Interrupt definition and position (continued)

Position Priority

Acronym

Description

STCOM10 データシート(PDF) 14 Page - STMicroelectronics

STCOM10 データシート(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

データシートダウンロード