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AD7912/AD7922

Rev. 0 | Page 17 of 32

Table 7 provides some typical performance data with various

op amps used as the input buffer, and a 50 kHz input tone under

the same setup conditions.

Table 7. AD7922 Performance for Various Input Buffers

Op Amp in the Input

Buffer

AD7922 SNR Performance (dB)

50 kHz Input , VDD = 3.6 V

Single op amps

AD8038

−72.79

AD8510

−72.35

AD8021

−72.2

Dual op amps

AD712

−72.68

AD8022

−72.88

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum

source impedance depends on the amount of total harmonic

distortion (THD) that can be tolerated. The THD increases as

the source impedance increases and performance degrades (see

Figure 16).

DIGITAL INPUTS

The digital inputs applied to the AD7912/AD7922 are not

limited by the maximum ratings that limit the analog input.

Instead, the digital inputs applied can go to 7 V and are not

restricted by the VDD + 0.3 V limit as on the analog input. For

example, if the AD7912/AD7922 are operated with a VDD of 3 V,

then 5 V logic levels could be used on the digital inputs. How-

ever, it is important to note that the data output on DOUT still

has 3 V logic levels when VDD = 3 V. Another advantage of

SCLK, DIN, and CS not being restricted by the VDD + 0.3 V limit

is that power supply sequencing issues are avoided. If CS, DIN,

or SCLK are applied before VDD, then there is no risk of latch-up

as there would be on the analog inputs if a signal greater than

0.3 V were applied prior to VDD.

DIN INPUT

The channel to be converted on in the next conversion is

selected by writing to the DIN pin. Data on the DIN pin is

loaded into the AD7912/AD7922 on the falling edge of SCLK.

The data is transferred into the part on the DIN pin at the same

time that the conversion result is read from the part. Only the

third and fourth bits of the DIN word are used; the rest are

ignored by the ADC.

The third MSB is the channel identifier bit, which identifies the

channel to be converted on in the next conversion,

VIN0 (CHN = 0) or VIN1 (CHN = 1).

The fourth MSB, STY, is related to the mode of operation of the

device. To keep the AD7912/ AD7922 in daisy-chain mode, the

CHN and STY bits have to be inverted during the conversions

(STY ≠ CHN). A conversion with STY = CHN on the input

forces the device to normal mode in the next cycle. See the

Daisy-Chain Mode section for more details.

If the AD7912/AD7922 are not going to be used in daisy-chain

mode, it is recommended to keep STY and CHN the same

(STY = CHN). In that case, the channel can be selected by tying

DIN either high or low during a conversion cycle.

To summarize:

CHN = 0

, Channel 0 selected for next conversion.

CHN = 1

, Channel 1 selected for next conversion.

CHN = STY

, forces normal mode in the next cycle.

CHN

≠ STY, keeps the AD7912/AD7922 in daisy-chain mode.

LSB

MSB

CHN

STY

DON'T CARE

Figure 24. AD7912/AD7922 DIN Word

DOUT OUTPUT

The conversion result from the AD7912/AD7922 is provided on

this output as a serial data stream. The bits are clocked out on

the SCLK falling edge at the same time that the conversion is

taking place.

The serial data stream for the AD7922 consists of two leading

zeros followed by the bit that identifies the channel converted,

the bit that indicates the current mode of operation, and the

12-bit conversion result with MSB provided first.

For the AD7912, the serial data stream consists of two leading

zeros followed by the bit that identifies the channel converted,

the bit that indicates the current mode of operation, and the

10-bit conversion result with MSB provided first, followed by

two trailing zeros.

The CHN and MOD bits on DOUT indicate to the user the

current mode of operation of the ADC. If CHN = MOD,

the AD7912/AD7922 are in normal mode. Otherwise, if

CHN ≠ MOD, the AD7912/AD7922 are in daisy-chain mode.

LSB

AD7912

MSB

CHN

MOD CONVERSION RESULT

AD7922

CHN

MOD

CONVERSION RESULT

Figure 25. AD7912/AD7922 DOUT Word

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