AD7912AUJ-R2 datasheet(18/32 Pages) AD

18 / 32 page

AD7912/AD7922

Rev. 0 | Page 18 of 32

MODES OF OPERATION

The three modes of operation of the AD7912/AD7922 are

normal mode, power-down mode, and daisy-chain mode. The

mode of operation is selected by controlling the logic state of

the CS signal. The point at which CS is pulled high after the

conversion has been initiated determines whether the

AD7912/AD7922 enter power-down mode or change to daisy-

chain mode. Similarly, if already in daisy-chain mode, CS can

control whether the device returns to normal operation or

enters power-down mode. The user can also change from daisy-

chain mode to normal mode by writing to the DIN pin, as

outlined in the DIN Input section.

Power-down mode is designed to provide flexible power

management options and to optimize the ratio of power

dissipation to throughput rate for different application

requirements.

Daisy-chain mode is intended for applications where fast

throughput rate is not required and more than one

AD7912/AD7922 have been connected in a daisy chain, as

shown in Figure 33.

NORMAL MODE

Normal mode is intended for the fastest throughput rate

performance. The user does not have to worry about any

power-up time, because the AD7912/AD7922 remain fully

powered all the time. Figure 26 shows the operation of the

AD7912/AD7922 in this mode.

The conversion is initiated on the falling edge of CS as

described in the Serial Interface section. To ensure that the part

remains fully powered up at all times, CS must remain low until

at least 10 SCLK falling edges have elapsed after the falling edge

of CS. If CS is brought high after the 10th SCLK falling edge

and before the 12th SCLK falling edge, then the device enters

daisy-chain mode, as shown in Figure 27. The conversion is

terminated and DOUT goes back into three-state. If CS is

brought high after the 13th SCLK falling edge, but before the

end of tCONVERT, the conversion is terminated and DOUT goes

back into three-state, but the part remains in normal mode.

For the AD7922, 16 serial clock cycles are required to complete

the conversion and access the complete conversion result. For

the AD7912, a minimum of 14 serial clock cycles are required

to complete the conversion and access the complete

conversion result.

CS can idle high until the next conversion or can idle low until

CS returns high sometime prior to the next conversion

(effectively idling CS low). Once a data transfer is complete

(DOUT has returned to three-state), another conversion can be

initiated after the quiet time, tQUIET, has elapsed by bringing CS

low again.

POWER-DOWN MODE

Power-down mode is intended for use in applications where

slower throughput rates are required. Either the ADC is

powered down between each conversion, or a series of

conversions can be performed at a high throughput rate and

then the ADC is powered down for a relatively long duration

between these bursts of several conversions. When the AD7912/

AD7922 are in power-down mode, all analog circuitry is

powered down.

To enter power-down mode, the conversion process must be

interrupted by bringing CS high any time after the second

falling edge of SCLK and before the 10th falling edge of SCLK,

as shown in Figure 28. Once CS has been brought high in this

window of SCLKs, then the part enters power-down mode, the

conversion that was initiated by the falling edge of CS is termi-

nated, and DOUT goes back into three-state. If CS is brought

high before the second SCLK falling edge, then the part remains

in normal mode and does not power down. This helps to avoid

accidental power-down due to glitches on the CS line.

To exit this mode of operation and power the AD7912/AD7922

up again, a dummy conversion is performed. On the falling edge

of CS, the device begins to power up and continues to power up

as long as CS is held low until after the falling edge of the

10th SCLK. The device is fully powered up once 16 SCLKs have

elapsed and valid data results from the next conversion, as

shown in Figure 29. If CS is brought high before the 10th falling

edge of SCLK, then the AD7912/AD7922 go back into power-

down mode. This helps to avoid accidental power-up due to

glitches on the CS line or an inadvertent burst of 8 SCLK cycles

while CS is low. Therefore, although the device might begin to

power up on the falling edge of CS, it powers down again on the

rising edge of CS, as long as this occurs before the 10th SCLK

falling edge.

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