AM79C970 datasheet(110/168 Pages) AMD

110 / 168 page

P R E L I M I N A R Y

AMD

1-977

Am79C970

BCR0: Master Mode Read Active

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 MSRDA

Reserved locations. After H_RE-

SET, the value in this register will

be 0005h. The settings of this

PCnet-PCI controller function.

Writes to this register have no ef-

fect on the operation of the

PCnet-PCI controller and will not

alter the value that is read.

BCR1: Master Mode Write Active

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 MSWRA

Reserved locations. After H_RE-

SET, the value in this register will

be 0005h. The settings of this

PCnet-PCI controller function.

Writes to this register have no ef-

fect on the operation of the

PCnet-PCI controller and will not

alter the value that is read.

BCR2: Miscellaneous Configuration

Bit

Name

Description

Note that all bits in this register

are programmable through the

EEPROM PREAD operation.

31–16 RES

Reserved locations. Written as

ZEROs and read as undefined.

RES

Reserved location. Written and

read as ZERO.

14 TMAULOOP

When set, this bit allows external

loopback packets to pass onto

the network through the TMAU

interface, if the TMAU interface

has been selected. If the TMAU

interface has not been selected,

then this bit has no effect.

This bit is reset to ZERO by

H_RESET and is unaffected by

S_RESET or STOP.

13–9

RES

Reserved locations. Written and

read as ZERO.

IESRWE

IEEE Shadow Ram Write En-

able. The PCnet-PCI controller

contains a shadow RAM on

board for storage of the IEEE ad-

dress

following

the

serial

EEPROM read operation. Ac-

cesses

APROM

I/O

Re-

sources will be directed toward

this RAM. When IESRWE is set

to a ONE, then write access to

the shadow RAM will be enabled.

This bit is reset to ZERO by

H_RESET and is unaffected by

S_RESET or STOP.

RES

Reserved location. The default of

this bit is zero. Writing a ONE to

this bit has no effect on the op-

eration

the

PCnet-PCI

controller.

This reserved location is cleared

by H_RESET and is unaffected

by S_RESET or STOP.

6–3

RES

Reserved locations. Written and

read as ZERO.

AWAKE

This bit selects one of two differ-

ent sleep modes.

If AWAKE=1 and the

SLEEP pin

is asserted, the PCnet-PCI con-

troller goes into snooze mode. If

AWAKE=0 and the

SLEEP pin is

asserted, the PCnet-PCI control-

ler goes into coma mode. See

Power Saving Modes section for

more details.

This bit only has meaning when

the 10BASE-T network interface

is selected.

This bit is reset to ZERO by

H_RESET and is unaffected by

S_RESET or STOP.

ASEL

Auto Select. When set, the

PCnet-PCI controller will auto-

matically select the operating

media interface port. If ASEL has

been set to a ONE, then when the

10BASE-T transceiver is in the

link pass state (due to receiving

valid frame data and/or Link Test

pulses or the DLNKTST bit is

set), the 10BASE-T port will be

used. If ASEL has been set to a

ONE, then when the 10BASE-T

port is in the link fail state, the AUI

port will be used. Switching be-

tween the ports will not occur dur-

ing transmission, to avoid any

type of fragment generation.

When ASEL is set to ONE, Link

Beat Pulses will be transmitted

on the 10BASE-T port, regard-

less of the state of Link Status.

When ASEL is reset to ZERO,

Link Beat Pulses will only be

transmitted on the 10BASE-T

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