AM79C970 datasheet(114/168 Pages) AMD

114 / 168 page

P R E L I M I N A R Y

AMD

1-981

Am79C970

pin will be driven to a LOW level

whenever the OR of the enabled

signals is true and the LED pin

will be disabled and allowed to

float high whenever the OR of the

enabled signals is false. (i.e. the

LED output will be an Open Drain

output and the output value will

be the inverse of the LEDOUT

status bit.)

When this bit has the value ONE,

then the LED pin will be driven to

a HIGH level whenever the OR of

the enabled signals is true and

the LED pin will be driven to a

LOW level whenever the OR of

the enabled signals is false. (i.e.

the LED output will be a Totem

Pole output and the output value

will be the same polarity as the

LEDOUT status bit.)

The setting of this bit will not af-

fect the polarity of the LEDOUT

bit for this register.

LEDDIS

LED Disable. This bit is used to

disable the LED output. When

LEDDIS has the value ONE, then

the LED output will always be

tristated. When LEDDIS has the

value ZERO, then the LED out-

put value will be governed by the

LEDOUT and LEDPOL values.

12–8

RES

Reserved locations. Write as ZE-

ROS, read as undefined.

A value of 0 disables the signal.

A value of 1 enables the signal.

PSE

Pulse Stretcher Enable. Extends

the LED illumination time for

each new occurrence of the en-

abled function for this LED

output.

A value of 0 disables the signal.

A value of 1 enables the signal.

LNKSTE

Link Status Enable. Indicates the

current link status on the Twisted

Pair interface. When this bit is en-

abled, a value of ONE will be

passed to the LEDOUT signal to

indicate that the link status state

is PASS. A value of ZERO will be

passed to the LEDOUT signal to

indicate that the link status state

is FAIL.

A value of 0 disables the signal.

A value of 1 enables the signal.

RCVME

Receive Match status Enable. In-

dicates receive activity on the

network that has passed the ad-

dress match function for this

node.

All

address

matching

modes are included: Physical,

Logical

filtering

and

Promiscuous.

A value of 0 disables the signal.

A value of 1 enables the signal.

XMTE

Transmit status Enable. Indi-

cates

PCnet-PCI

controller

transmit activity.

A value of 0 disables the signal.

A value of 1 enables the signal.

RXPOLE

Receive Polarity status Enable.

Indicates the current Receive

Polarity condition on the Twisted

Pair interface. A value of ONE in-

dicates that the polarity of the

RXD

± pair has been reversed. A

value of ZERO indicates that the

polarity of the RXD

± pair has not

been reversed.

Receive polarity indication is

valid only if the T-MAU is in the

Link Pass state.

A value of 0 disables the signal.

A value of 1 enables the signal.

RCVE

Receive status Enable. Indicates

receive activity on the network.

A value of 0 disables the signal.

A value of 1 enables the signal.

JABE

Jabber status Enable. Indicates

that the PCnet-PCI controller is

jabbering on the network.

A value of 0 disables the signal.

A value of 1 enables the signal.

COLE

Collision status Enable.

Indi-

cates collision activity on the net-

work.

A value of 0 disables the signal.

A value of 1 enables the signal.

BCR16: I/O Base Address Lower

Bit

Name

Description

Note that all bits in this register

are programmable through the

EEPROM PREAD operation.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–5 IOBASEL

Reserved locations. After H_RE-

SET, the value of these bits will

be undefined. The settings of

these bits will have no affect on

any

PCnet-PCI

controller

function.

IOBASEL is not affected by

S_RESET or STOP.

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