AM79C970 datasheet(115/168 Pages) AMD

115 / 168 page

AMD

P R E L I M I N A R Y

1-982

Am79C970

4–0

RES

Reserved locations. Written as

ZEROS, read as undefined.

BCR17: I/O Base Address Upper

Bit

Name

Description

Note that all bits in this register

are programmable through the

EEPROM PREAD operation.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 IOBASEU

Reserved locations. After H_RE-

SET, the value in this register will

be undefined. The settings of this

PCnet-PCI controller function.

IOBASEU is not affected by

S_RESET or STOP.

BCR18: Burst Size and Bus Control

Bit

Name

Description

Note that all bits, except bit 7, in

this register are programmable

through the EEPROM PREAD

operation.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–11

RES

Reserved locations. After H_RE-

SET, these five bits will read

00100b. The settings of these

bits will have no affect on any

PCnet-PCI controller function.

Writes to these bits have no af-

fect on the operation of PCnet-

PCI controller.

RES is set to 00100b by H_RE-

SET and is not affected by

S_RESET or STOP.

RES

Reserved location. Must be writ-

ten as ZERO. Writing a one to

this bit may cause the PCnet-PCI

controller to malfunction in a

system.

This reserved location is cleared

by H_RESET and is not affected

by S_RESET or STOP.

RES

Reserved location. Written as

ZERO and read as undefined.

This reserved location is cleared

by H_RESET and is not affected

by S_RESET or STOP.

RES

Reserved bit. Must be written as

a ONE. Will be read as a ONE.

This reserved location is SET by

H_RESET and is not affected by

S_RESET or STOP.

DWIO

Double Word I/O. When set, this

bit indicates that the PCnet-PCI

controller is programmed for

DWIO mode. When cleared, this

bit indicates that the PCnet-PCI

controller is programmed for

Word I/O mode. This bit affects

the I/O Resource Offset map and

it affects the defined width of the

PCnet-PCI controller’s I/O re-

sources. See the DWIO and WIO

sections for more details.

The PCnet-PCI controller will set

DWIO if it detects a DWORD

write access to offset 10h from

the PCnet-PCI controller I/O

base address (corresponding to

the RDP resource). A double-

word write access to offset 10h is

the only way that the DWIO bit

can be set. DWIO cannot be set

by a direct write to BCR18.

Once the DWIO bit has been set

to a ONE, only a H_RESET can

reset it to a ZERO.

DWIO is read only by the host.

DWIO is cleared by H_RESET

and is not affected by S_RESET

or STOP.

BREADE

Burst Read Enable. When set,

this bit enables Linear Bursting

during memory read accesses,

where Linear Bursting is defined

to mean that only the first transfer

in the current bus arbitration will

contain an address phase. Sub-

sequent transfers will consist of

data phases only. When cleared,

this bit prevents the part from

performing linear bursting during

read accesses. In no case will the

part linearly burst a descriptor ac-

cess or an initialization access.

BREADE should be set to ONE

when the PCnet-PCI controller is

used in a PCI bus application.

The use of burst transfers guar-

antees maximum performance

during memory read operations.

BREADE is cleared by H_RE-

SET and is not affected by S_RE-

SET or STOP.

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