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ST7DALIF2 データシート(PDF) 99 Page - STMicroelectronics

部品番号 ST7DALIF2
部品情報  Configurable watchdog timer
PDF  171 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 データシート(HTML) 99 Page - STMicroelectronics

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ST7DALIF2
DALI communication module
99/171
0: The DCM is in Transmit state
1: The DCM is in Receive state
Bits 3:0 = DCMCSR[3:0] Clock counter value. (Read only) These bits are set/cleared by
hardware and read by software.
The value of the 4-bit sample clock counter (integer range 0 to 15). The clock counter value
is loaded in the DCMCSR register when a DALI change of phase signal is detected (edge
trigger). Refer to Figure 44.
Table 45.
Register map and reset values
Address
(Hex.)
Register
label
7654
3210
0040h
DCMCLK
Reset
Value
CK7
0
CK6
0
CK5
0
CK4
0
CK3
0
CK2
0
CK1
0
CK0
0
0041h
DCMFA
Reset
Value
FA7
0
FA6
0
FA5
0
FA4
0
FA3
0
FA2
0
FA1
0
FA0
0
0042h
DCMFD
Reset
Value
FD7
0
FD6
0
FD5
0
FD4
0
FD3
0
FD2
0
FD1
0
FD0
0
0043h
DCMBD
Reset
Value
BD7
0
BD6
0
BD5
0
BD4
0
BD3
0
BD2
0
BD1
0
BD0
0
0044h
DCMCR
Reset
Value
0000
DCME
0
RTA
0
RTS
0
FTS
0
0045h
DCMCSR
Reset
Value
ITE
0
ITF
0
EF
0
RTF
0
CK3
0
CK2
0
CK1
0
CK0
0



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