ST7DALIF2 datasheet(39/171 Pages) STMICROELECTRONICS

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ST7DALIF2

Supply, reset and clock management

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9.6.2

Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up

resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See Electrical Characteristic

section for more details.

A RESET signal originating from an external source must have a duration of at least

th(RSTL)in in order to be recognized (see Figure 15). This detection is asynchronous and

therefore the MCU can enter reset state even in Halt mode.

Figure 14.

Reset block diagram

Note:

Illegal Opcode Reset on page 124 for more details on illegal opcode reset conditions.

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In

a noisy environment, it is recommended to follow the guidelines mentioned in the electrical

characteristics section.

9.6.3

External power-on RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must

ensure by means of an external reset circuit that the reset signal is held low until VDD is over

the minimum level specified for the selected fOSC frequency.

A proper reset signal for a slow rising VDD supply can generally be provided by an external

RC network connected to the RESET pin.

9.6.4

Internal low voltage detector (LVD) RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

●

Power-on RESET

●

Voltage drop RESET

The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or

VDD<VIT- (falling edge) as shown in Figure 15.

The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

PULSE

GENERATOR

Filter

ILLEGAL OPCODE RESET

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