STM32L063C8 datasheet(33/121 Pages) STMICROELECTRONICS

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STM32L063x8

Functional overview

3.19.6

Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

3.20

Communication interfaces

3.20.1

I2C bus

two I2C interface (I2C1, I2C2) can operate in multimaster or slave modes.

Each I2C interface can support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to

400 kbit/s) and Fast Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.

7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with

configurable mask) are also supported as well as programmable analog and digital noise

filters.

In addition, I2C1 provides hardware support for SMBus 2.0 and PMBus 1.1: ARP capability,

Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and

ALERT protocol management. I2C1 also has a clock domain independent from the CPU

clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.

Each I2C interface can be served by the DMA controller.

Refer to Table 11 for an overview of I2C interface features.

Table 10. Comparison of I2C analog and digital filters

Analog filter

Digital filter

Pulse width of

suppressed spikes

≥ 50 ns

Programmable length from 1 to 15

I2C peripheral clocks

Benefits

Available in Stop mode

1. Extra filtering capability vs.

standard requirements.



2. Stable length

Drawbacks

Variations depending on

temperature, voltage, process

Wakeup from Stop on address

match is not available when digital

filter is enabled.

Table 11. STM32L063x8 I2C implementation

I2C features(1)

I2C1

I2C2

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

X(2)

Independent clock

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