AS4C64M8D2 datasheet(10/59 Pages) ALSC

10 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

 Extended Mode Register Set (EMRS)

- EMR(1)

The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT

value selection and additive latency. The default value of the extended mode register is not defined, therefore the

extended mode register must be written after power-up for proper operation. The extended mode register is

written by asserting LOW on CS#, RAS#, CAS#, WE#, BA1 and HIGH on BA0, while controlling the states of

address pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to

writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to

complete the write operation to the extended mode register. Mode register contents can be changed using the

same command and clock cycle requirements during normal operation as long as all banks are in the precharge

state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength data-output driver. A3~A5

determine the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used for OCD control,

A10 is used for DQS# disable.

- DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon

returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self

refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled

(and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for

the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may

result in a violation of the tAC or tDQSCK parameters.

Table 6. Extended Mode Register EMR (1) Bitmap

BA1 BA0 A13 A12 A11 A10 A9

A0 Address Field

Qoff 0

DQS#

OCD program Rtt Additive Latency Rtt D.I.C DLL Extended Mode Register

BA1

BA0

MRS mode

Rtt(NOMINAL)

ODT Disable

DLL Enable

EMR(1)

75Ω

Enable

EMR(2)

150Ω

Disable

EMR(3)

50Ω

A7 OCD Calibration Program

Output Driver

Impedance Control

OCD Calibration mode exit; maintain setting

Reserved

Full strength

Reserved

Reduced strength

Reserved

OCD Calibration default

Additive Latency

A12

Qoff

Output buffer enabled

A10

DQS#

Output buffer disabled

Enable

Disable

Reserved

NOTE 1: After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000.

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