AS4C64M8D2 datasheet(11/59 Pages) ALSC

11 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

NOTE 2: Output disabled – DQs, DQSs, DQSs#. This feature is intended to be used during IDD characterization of read

current.

NOTE 3: A11, A13 are reserved for future use and must be set to 0 when programming the MR.

- EMR(2)

The extended mode register (2) controls refresh related features. The default value of the extended mode

operation. The extended mode register(2) is written by asserting LOW on CS#, RAS#, CAS#, WE#, HIGH on

BA1 and LOW on BA0, while controlling the states of address pins A0 ~ A13. The DDR2 SDRAM should be in all

bank precharge with CKE already HIGH prior to writing into the extended mode register (2). The mode register

set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register

(2). Mode register contents can be changed using the same command and clock cycle requirements during

normal operation as long as all banks are in the precharge state.

Table 7. Extended Mode Register EMR(2) Bitmap

BA1 BA0 A13 A12 A11 A10 A9

A0 Address Field

SRF

Extended Mode Register(2)

High Temperature Self-Refresh Rate Enable

Disable

Enable

NOTE 1: The rest bits in EMRS(2) are reserved for future use and all bits in EMRS(2) except A7, BA0 and BA1 must be

programmed to 0 when setting the extended mode register(2) during initialization.

NOTE 2: Due to the migration nature, user needs to ensure the DRAM part supports higher than 85℃ Tcase temperature

self-refresh entry. If the high temperature self-refresh mode is supported then controller can set the EMRS2[A7] bit

to enable the self-refresh rate in case of higher than 85℃ temperature self-refresh operation.

AS4C64M8D2 データシート(PDF) 11 Page - Alliance Semiconductor Corporation