AS4C64M8D2 datasheet(36/59 Pages) ALSC

36 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

Figure 13.ODT timing mode switch at exit power-down mode

CK#

tIS

CKE

tAOFD

tAOND

ODT

tAXPD

T10

T11

Exiting from Slow Active Power Down Mode or Precharge power Down Mode.

Internal

Term Res.

tIS

VIL(ac)

ODT

Internal

Term Res.

tIS

VIL(ac)

Active & Standby mode

timings to be applied.

Power Down mode

timings to be applied.

tIS

VIH(ac)

Active & Standby mode

timings to be applied.

tAONPD max

tIS

VIH(ac)

Power Down mode

timings to be applied.

ODT

Internal

Term Res.

Internal

Term Res.

RTT

tAOFPD max

VIH(ac)

RTT

Figure 14. Bank activate command cycle (tRCD=3, AL=2, tRP=3, tRRD=2, tCCD=2)

CK#

Tn+1

Tn+2

Internal RAS# - CAS# delay (>=tRCD min)

CAS# - CAS# delay time (tCCD)

tRCD = 1

Read Begins

Tn+3

Bank A

Row Addr.

Bank A

Col. Addr.

Bank B

Row Addr.

Bank B

Col. Addr

Bank A

Addr.

Bank B

Addr.

Bank A

Row Addr.

Additive latency delay (AL)

Bank A

Activate

Bank A

Post CAS#

Read

Bank B

Activate

Bank B

Post CAS#

Read

Bank A

Precharge

Bank B

Precharge

Bank A

Activate

RAS# - RAS# delay time (>=tRRD)

Bank Active (>=tRAS)

Bank precharge time (>=tRP)

RAS# Cycle time (>=tRC)

ADDRESS

COMMAND

AS4C64M8D2 データシート(PDF) 36 Page - Alliance Semiconductor Corporation

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