AD9268-80EBZ datasheet(16/45 Pages) AD

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AD9268

Rev. A | Page 15 of 44

PIN 1

INDICATOR

CLK+

CLK–

SYNC

D0– (LSB)

D0+ (LSB)

D1–

D1+

D2–

D2+

DRVDD

D3–

D3+

D4–

D4+

D5–

D5+

PDWN

OEB

CSB

SCLK/DFS

SDIO/DCS

OR+

OR–

D15+ (MSB)

D15– (MSB)

D14+

D14–

DRVDD

D13+

D13–

D12+

D12–

AD9268

PARALLEL LVDS

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE

PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED

PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)

Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

10, 19, 28, 37

DRVDD

Supply

Digital Output Driver Supply (1.8 V Nominal).

49, 50, 53, 54, 59,

60, 63, 64

AVDD

Supply

Analog Power Supply (1.8 V Nominal).

AGND,

Exposed Pad

Ground

The exposed thermal pad on the bottom of the package provides the analog

ground for the part. This exposed pad must be connected to ground for proper

operation.

ADC Analog

VIN+A

Input

Differential Analog Input Pin (+) for Channel A.

VIN−A

Input

Differential Analog Input Pin (−) for Channel A.

VIN+B

Input

Differential Analog Input Pin (+) for Channel B.

VIN−B

Input

Differential Analog Input Pin (−) for Channel B.

VREF

Input/Output

Voltage Reference Input/Output.

SENSE

Input

Voltage Reference Mode Select. See Table 11 for details.

RBIAS

Input/Output

External Reference Bias Resistor.

VCM

Output

Common-Mode Level Bias Output for Analog Inputs.

CLK+

Input

ADC Clock Input—True.

CLK−

Input

ADC Clock Input—Complement.

Digital Input

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

D0+ (LSB)

Output

Channel A/Channel B LVDS Output Data 0—True.

D0− (LSB)

Output

Channel A/Channel B LVDS Output Data 0—Complement.

D1+

Output

Channel A/Channel B LVDS Output Data 1—True.

D1−

Output

Channel A/Channel B LVDS Output Data 1—Complement.

D2+

Output

Channel A/Channel B LVDS Output Data 2—True.

D2−

Output

Channel A/Channel B LVDS Output Data 2—Complement.

D3+

Output

Channel A/Channel B LVDS Output Data 3—True.

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