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AD9268-80EBZ データシート(PDF) 17 Page - Analog Devices

部品番号 AD9268-80EBZ
部品情報  1.8 V Dual Analog-to-Digital Converter (ADC)
PDF  45 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9268-80EBZ データシート(HTML) 17 Page - Analog Devices

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AD9268
Rev. A | Page 16 of 44
Pin No.
Mnemonic
Type
Description
11
D3−
Output
Channel A/Channel B LVDS Output Data 3—Complement.
14
D4+
Output
Channel A/Channel B LVDS Output Data 4—True.
13
D4−
Output
Channel A/Channel B LVDS Output Data 4—Complement.
16
D5+
Output
Channel A/Channel B LVDS Output Data 5—True.
15
D5−
Output
Channel A/Channel B LVDS Output Data 5—Complement.
18
D6+
Output
Channel A/Channel B LVDS Output Data 6—True.
17
D6−
Output
Channel A/Channel B LVDS Output Data 6—Complement.
21
D7+
Output
Channel A/Channel B LVDS Output Data 7—True.
20
D7−
Output
Channel A/Channel B LVDS Output Data 7—Complement.
23
D8+
Output
Channel A/Channel B LVDS Output Data 8—True.
22
D8−
Output
Channel A/Channel B LVDS Output Data 8—Complement.
27
D9+
Output
Channel A/Channel B LVDS Output Data 9—True.
26
D9−
Output
Channel A/Channel B LVDS Output Data 9—Complement.
30
D10+
Output
Channel A/Channel B LVDS Output Data 10—True.
29
D10−
Output
Channel A/Channel B LVDS Output Data 10—Complement.
32
D11+
Output
Channel A/Channel B LVDS Output Data 11—True.
31
D11−
Output
Channel A/Channel B LVDS Output Data 11—Complement.
34
D12+
Output
Channel A/Channel B LVDS Output Data 12—True.
33
D12−
Output
Channel A/Channel B LVDS Output Data 12—Complement.
36
D13+
Output
Channel A/Channel B LVDS Output Data 13—True.
35
D13−
Output
Channel A/Channel B LVDS Output Data 13—Complement.
39
D14+
Output
Channel A/Channel B LVDS Output Data 14—True.
38
D14−
Output
Channel A/Channel B LVDS Output Data 14—Complement.
41
D15+ (MSB)
Output
Channel A/Channel B LVDS Output Data 15—True.
40
D15− (MSB)
Output
Channel A/Channel B LVDS Output Data 15—Complement.
43
OR+
Output
Channel A/Channel B LVDS Overrange Output—True.
42
OR−
Output
Channel A/Channel B LVDS Overrange Output—Complement.
25
DCO+
Output
Channel A/Channel B LVDS Data Clock Output—True.
24
DCO−
Output
Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control
45
SCLK/DFS
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
44
SDIO/DCS
Input/Output
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
46
CSB
Input
SPI Chip Select (Active Low).
ADC Configuration
47
OEB
Input
Output Enable Input (Active Low) in External Pin Mode.
48
PDWN
Input
Power-Down Input in External Pin Mode. In SPI mode, this input can be
configured as power-down or standby.



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