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AM652X データシート(PDF) 235 Page - Texas Instruments |
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AM652X データシート(HTML) 235 Page - Texas Instruments |
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235 / 299 page  TDO J2 J1 J4 TCK J5 TDI / TMS J3 J6 J7 J4 J5 235 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Table 5-125. Timing Requirements for IEEE 1149.1 JTAG (continued) NO. PARAMETER DESCRIPTION MIN MAX UNIT J4 tsu(TDI-TCK) Input setup time minimum, TDI valid to TCK high 8 ns tsu(TMS-TCK) Input setup time minimum, TMS valid to TCK high 8 ns J5 th(TCK-TDI) Input hold time minimum, TDI valid from TCK high 5.2 ns th(TCK-TMS) Input hold time minimum, TMS valid from TCK high 5.2 ns Table 5-126. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT J6 td(TCKL-TDOI) Delay time minimum, TCK low to TDO invalid 0 ns J7 td(TCKL-TDOV) Delay time maximum, TCK low to TDO valid 27.75 ns Figure 5-132. JTAG Test-Port Timing |
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