AM652X datasheet(239/299 Pages) TI1

239 / 299 page

239

AM6548, AM6528, AM6546

AM6526, AM6527

www.ti.com

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

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Cortex-A53 MPCore (A53 Cluster) features:

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Dual-core configuration (coherent SMP processors within the cluster)

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Full compliance to Armv8-A architecture

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AArch32 and AArch64 Execution States

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AArch32 for full backward compatibility with Armv7

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AArch64 for 64b support and new architectural features

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All exception levels EL0-3

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A32 Instruction Set

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T32 Instruction Set

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A64 Instruction Set

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NEON Advanced SIMD

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VFPv4 Floating point

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Hardware virtualization support

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Armv8 Cryptography Extensions

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Arm GICv3 architecture

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In-order pipeline with symmetric dual-issue of most instructions

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Harvard L1 with system MMU

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32KB Instruction (Program) Cache

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32KB Data Cache

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512KB Shared L2 Cache

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Snoop Control Unit (SCU) managing the interconnect, arbitration, communication, cache-to-cache

and system memory transfers, cache coherence and other capabilities for the processor

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Generic Timer(s)

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Arm CoreSight™ Debug and Trace Architecture

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Functional safety support

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Error Correction Code (ECC) protection for:

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L1 Data Cache (Data RAM)

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L2 Cache (Data RAM, Tag RAM)

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L1 SCU Duplicate Tags

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Parity protection for:

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L1 Instruction Cache (Data RAM and Tag RAM)

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L1 Data Cache Tag RAM and Dirty Bits

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TLB

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No error protection on branch protection and L2 victim RAM

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Support for error injection to all supported ECC memory blocks

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Provided for testing ECC functionality in safety-critical applications (add-on function from TI)

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Supported by ECC Aggregators at the CC_ARMSS level

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256-bit wide, synchronous or asynchronous VBUSM.C master interface

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AXI2VBUSM_MASTER Bridge

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Sync/Async boot time selectable via pin

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Cache pre-warming via use of ACP Port

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64-bit graycoded system input time

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48-bit graycoded debug input time

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32-bit VBUSP slave interface for debug (internally converted to APB)

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32-bit ATB output port for debug/trace

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Interface with Arm GIC-500 Interrupt Controller (SoC level, not part of CC_ARMSS)

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Supports the SoC multi-core cache coherency architecture

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