AM652X datasheet(238/299 Pages) TI1

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AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Detailed Description

6.3

Arm Cortex-A53

The SoC implements two Dual-Core Arm Cortex-A53 Subsystems (CC_ARMSS0 and CC_ARMSS1),

which are both integrated inside the Compute Cluster (along with the MSMC module). The Cortex-A53

cores are general-purpose processors that can be used for running customer applications.

NOTE

Notes on references used in this document:

•

Both Arm Cortex-A53 Subsystems are functionally identical and are referred to as a

single subsystem (CC_ARMSS), where appropriate.

•

CC_ARMSS is also referred to as Arm CorePac.

•

Cortex-A53 is often shortened to A53.

The CC_ARMSS is built around the Cortex-A53 MPCore (Arm A53 Cluster), which is provided by Arm and

configured by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus it delivers high

performance and optimal power management, debug and emulation capabilities.

The A53 processor is an Armv8A-compatible, multi-issue out-of-order superscalar execution engine with

integrated L1 Instruction and Data Caches. It delivers significantly more performance than its

predecessors at a higher level of power efficiency.

The Armv8-A architecture brings a number of new features. These include 64-bit data processing,

extended virtual addressing and 64-bit general purpose registers. The A53 processor is Arm’s first Armv8-

A processor aimed at providing power-efficient 64-bit processing. It features an in-order, 8-stage, dual-

issue pipeline, and improved integer, NEON™, Floating-Point Unit (FPU) and memory performance.

The A53 CPU supports two execution states: AArch32 and AArch64. The AArch64 state gives the A53

CPU its ability to execute 64-bit applications, while the AArch32 state allows the processor to execute

existing Armv7-A applications.

Details on the Compute Cluster module and the interaction between CC_ARMSS(s) and MSMC can be

found in the Compute Cluster chapter.

The CC_ARMSS supports the following key features:

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