AM652X datasheet(236/299 Pages) TI1

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236

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Detailed Description

6.1

Overview

AM654x and AM652x Sitara Arm applications processors are built to meet the complex processing needs

of modern industrial embedded products.

The AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dual Cortex-R5F

MCU subsystem which includes features intended to help customers achieve their functional safety goals

for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a

SoC capable of high-performance industrial controls with industrial connectivity and processing for

functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD

according to IEC 61508.

The four A53 cores are arranged in two dual-core clusters with shared L2 memory to create two

processing channels. Extensive ECC is included on on-chip memory, peripherals, and interconnect for

reliability. The SoC as a whole includes features intended to help customers design systems that can

achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and

secure boot are available on AM654x and AM652x devices in addition to granular firewalls managed by

the DMSC.

Programmability is provided by the quad-core Arm Cortex-A53 RISC CPUs with Neon extension, and the

dual Cortex-R5F MCU subsystem is available for general purpose use as two cores or it can be used in

lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be

used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, or EtherCAT™ (among

many others), or they can be used for standard Gigabit Ethernet connectivity.

TI provides a complete set of software and development tools for the Arm cores including Processor SDK

Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source

code execution. Applicable safety documentation will be made available to assist customers in developing

their functional safety related systems.

NOTE

For more information on features, subsystems, and architecture of superset device System

on Chip (SoC), see the device TRM.

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