FS970X datasheet(32/46 Pages) FORTUNE

32 / 46 page

FS970X

Rev. 4.4

32/46

in Graph 4. The frequency of the target can be obtained from the following formula:

Formula 12

INSIG





Whereas KSG and KTB are the values of signal counter and time-based counter respectively. FTB is the

frequency of reference signal, as shown in Chart 3. FINSIG is the frequency of the target signal.

When performing the duty cycle measurement, the relationship between the duty cycle DTINSIG and KSG 和 KTB

is as follow:

Formula 13

INSIG



100%

You may have noticed that the value is independent from the reference time pulse frequency.

The reading process of frequency counter

Both controls of frequency measurement and duty cycle measurement are the motion of the frequency counter

through FQRST_. When first setting FQRST_ to 0, and then resetting it to 1, it will trigger the action of

frequency counter. It will complete the counting in approx. 0.2 seconds. It will also advice the microprocessor

to read. After the reading of KTB and KSG, the value can be calculated from Formula 12 or Formula 13.

Then, repeat the reset to get the new value of the next measurement, and so forth and so on.

However, whether processed by the interrupt or polling after the reset of the counter, the interrupt status bit is

set to 1, meaning the counting is completed. However, when using the frequency counter of FS970X chip,

and when entering the counter measurement, after the first reset, it should read the values of KTB and KSG. It

doesn’t need to process the values. Thereafter, it starts the reading process of the interrupt status bits.

Peak-hold sampling process

As shown in the Chart 17, the reading of the output value of fast ADC meets the requirement of positive

negative peak-hold of pulse bandwidth measuring in a matter of naro-second. The peak-hold sampling logic of

FS970X accepts the control of PKHRST. It uses the SUM 2 as an input. It composed of the positive-negative

peak-hold comparison device and the positive-negative peak-hold register.

When PKHRST_ equals 0, the positive peak-hold register (POSPK) and the negative peak-hold register

(NEGPK) will be reset to the most negative and positive value respectively.

When PKHRST is set to Hi, the digit comparison device will compare the value of SUM2 with the value of the

positive peak-hold register (POSPK) and the negative peak-hold register (NEGPK). When the value of SUM2 is

greater than the value of the positive peak-hold register, the value of the positive peak-hold register will be

updated, otherwise it will remain the same. When the value of SUM2 is smaller than the value of the negative

peak-hold register, the value of the negative peak-hold register will be updated, otherwise it will remain the

same.

Therefore, after resetting the peak-hold sampling logic, set PKHRST_ equal 1, and the interrupt status digit of

the peak-hold sampling to 1; then, read the values of POSPK and NEGPK registers. One can obtain the values

of the measuring of positive peak-hold and negative peak-hold values.

Because the value of the peak-hold sampling device is derived from the value of SUM2, one should use

Formula 5 to calculate the equivalent voltage value of the operator.

FS970X データシート(PDF) 32 Page - Fortune Semiconductor Corp.

FS970X データシート(HTML) 32 Page - Fortune Semiconductor Corp.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

データシートダウンロード