FS970X datasheet(11/46 Pages) FORTUNE

11 / 46 page

FS970X

Rev. 4.4

11/46

Regulator

FS970x Regulator

REFH

GNDR

VDDP

S81250

OUT

20 uF

VDD

VSS

9V Battery

VBAT

AGND

20 uF

VCC

VDDP

ENGNDR_

VDD

Graph 1. FS970X Regulator Block-diagram

FS970X Regulator, as shown in Graph 1, needs to be connected with a S81250 low-cost regulator to convert

the battery voltage above 6.8V to VDD voltage of approx. 6.3V. There are two functions of VDD power: one is

the positive voltage (negative voltage to be VSSA) of analog circuit (or regulator), and the other is as the

reference voltage of regulators.

The power of the digital circuit in the chip is supplied by VCC. The digital signal ground is VSSD. The digital

signal ground VSSD and negative supply of analog circuit VSSA in the chip are connected by chip foundation of

thousand ohms.

As shown in Graph 1, the FS970X regulator circuit refers respectively to the voltage of VDDP and REFH; at the

same time, adjusting to the voltage of VCCR, GNDR and VSS to supply the chip. If VSS is set to be 0V, the

voltage of VCCR and GNDR will be 5V and 3.2V. This analog supply can directly supply AD737 to enable the

meter to measure the true root mean square of AC signal.

The supply source of FS970X can be selected by users, either from the chip itself or from external connection.

The analog supply within the chip is provided by VDDA, AGND and VSSA. Thus, directly feeding the output of

regulator VCCR, GNDR and VSS into VCC, AGND and VSSA will supply the chip itself. If the system has its

own supply, it can be connected directly to VCC, AGND and VSSA, instead of using VCCR and GNDR.

The power consumption of analog is static DC current, with an equivalent DC power consumption. The major

reason that will affect this DC power consumption is the change between each function. The power

consumption of FS970X analog parts is designed to be under 1.2mA and the digital parts under 0.5mA.

To be even more stringent on power consumption design under saving mode, connecting the chip’s analog

supply VDDA to VDDS will reduce the idle VDDA consumption to 0 under saving mode. For details about VDDS,

please see 5.3.

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