FS970X datasheet(36/46 Pages) FORTUNE

36 / 46 page

FS970X

Rev. 4.4

36/46

Measurement Registers

Address

Function

Length of

Times of

reading

KTB<23:0>

Output of time-based counter

KSG<23:0>

Output of signal counter

POSPK<15:0>

The up-most positive peak-hold register

NEGPK<15:0>

The up-most negative peak-hold register

SUM2<15:0>

Output of low-resolution ADC

SUM1<23:0>

Output of high-resolution ADC

Chart 21. all measurement value registers in the chip.

All measurement registers and their corresponding address of FS970X are listed in Chart 21. There are six

addresses in total. The length of each register varies. They are all output ports, and can only be read by

microprocessor.

The reading clocks of the measurement register are shown in

Graph . When IRQC<x> is on the negative-end, it will clear the corresponding INSTA<x>. The number of

readings of each new value has to be correct. Otherwise, read/write cycle counter CYCNTR will be cleared to

0 when ALE is “Hi”. The number of readings of each address varies with the length of each register, as shown

in the last column of Chart 21.

When reading SUM1or SUM2, the first reading period (when CYCNTR=1), the low pulse width of RD_ must be

greater than the sampling period of ADC. The other reading periods need only to be greater than 2 us. For

example, when the sampling frequency of the ADC is 83.3 kHz, then, the first reading period of SUM1 and

SUM2 must be greater than 12 us.

Regarding the frequency counter, what worth mentioning is when reading the value of the time-based counter,

it will not clear the interrupt bit INSTA<3>. Only when reading the signal counter, its corresponding interrupt

bit INSTA<3> can be cleared.

INSTA<2> will be cleared whether reading registers of the up-most positive peak-hold value or up-most

negative peak-hold value.

ALE

RD_

CS_

Address, 0A~0F

DATA<3:0>

READ MEASURED REGISTER CYCLE

DATA<N:N-3>

N/4

CYCNTR

DATA<N-4:N-7>

IRQC<x>

AD<3:0>

Graph 16. Reading sequence diagram of measuring registers.

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