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FS970X データシート(PDF) 35 Page - Fortune Semiconductor Corp. |
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FS970X データシート(HTML) 35 Page - Fortune Semiconductor Corp. |
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35 / 46 page  FS970X Rev. 4.4 35/46 The interrupt process The measurements can be read by the microprocessor interface are high-resolution output of ADC, the low resolution output of ADC, positive-negative peak-hold value, the output of frequency counter…etc. In any of the registers, each new value means new “event”. The chip, thru its IRQO pin, will send an interrupt signal to the microprocessor and request to process. When microprocessor received an interrupt signal of negative-end trigger; means that some measuring registers in 970x chip has detected a new value. The microprocessor will then read the interrupt status register （ INTSTA）, checking where the interrupt comes from. Chart 20 shows the corresponding event for each bit in the INSTA. The INTEN in Chart 20 controls whether a measuring event interrupt will occur. INSTA INSTA<3> INSTA<2> INSTA<1> INSTA<0> Event Frequency counter output +/- peak-hold value Low-resolution ADC High-resolution ADC INTEN INTEN<3> INTEN<2> INTEN<1> INTEN<0> Function Corresponding IRQO enable Corresponding IRQO enable Corresponding IRQO enable Corresponding IRQO enable Chart 20. Interrupt status registers. When microprocessor reads the register again, the interrupt bit will be reset to 0, and waiting for the new measurement to generate the interrupt again. The interrupt status register INSTA<3:0> is a read-only register. The interrupt enable register INTEN<3:0> is a read/write register. The read/write sequences of both registers are the same as control register, as shown in Graph 15. The flow-Chart of interrupt process are as follows: 1) When there’s a new value shown in the enable register, then set IRQO equal to 0, and keep it to 0. 2) When microprocessor receive this negative-end trigger, then read the interrupt status register. 3) After reading the status register, IRQO will be pulled back to1. 4) Check if the IRQO was pulled back to 1. If not, it means that it didn’t catch a negative end; then, it should read the interrupt status one more time. When reading the instruction period of the interrupt register; the negative-end of the new interrupt might be lost. Therefore, by adding Step 4) will improve this problem. In addition, whether the value of the interrupt status register has been updated in independent from interrupt enable register. That is to say, the interrupt enable register only affects IRQO output. |
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