FS970X datasheet(12/46 Pages) FORTUNE

12 / 46 page

FS970X

Rev. 4.4

12/46

Low Voltage Detector

360K

303K

LBS

CMP

AGND

LBO

ENLBS

BATTER

VSSD

VBAT

Graph 2

Low Voltage Detector

Low voltage detector is shown as Graph 2. After the voltage of VBAT is divided as LBS by resistor, it will flow

into low voltage detector. The output of the detector is LBO, used to judge whether the battery voltage VBAT is

lower than 6.8V. If it’s lower than 6.8V, the output is “Hi”, me

aning that it needs a battery change. Before

reading LBO, set ENLBS to “Hi”. After approx. 0.1 ms, pull it back to “L” to read LBO.

The voltage of LBS can flow into ADC, controlled by ADC multiplexers. It can also be directly measured by ADC.

The battery voltage is calculated as Formula 1.

Formula 1 .....................................................

LBS

BAT





Under saving mode, setting ENGNDR_ (MISC2<1>) to “H” will turn off GNDR in order to save power

consumption.

Saving Mode

In FS970X, all the power-consumption related circuits, except for VCCR generator, can be turned off by

FS970X registers to save power. The power-consumption related control signals and components are shown in

Chart 2.

If all of the FS970X components are turned off, only VCCR regulator will still be running. This keeps the chip

power consumption under 10 uA.

According to the setup in Chart 2, the power consumption of VDDA may drift. Therefore, aside from the setup

procedures in Chart 2, the supply of VDDA should come from VDDS considering the saving mode. By doing

so, S81250 will be the only component that consumes power under saving mode.

Control circuit

Saving mode value

Related power

consumption circuit

RGD>3:0>

MODE<3:0>

000x

Fixed voltage generator

SRF<7:6>

SOSR<1:0>

Ohm power supply

SCP<0>

CMPEN1

Comparator

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