AM29BDS643D datasheet(17/46 Pages) AMD

17 / 46 page

Am29BDS643D

PRELI M INARY

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 4 defines the valid register command

sequences. Writing incorrect address and data

values or writing them in the improper sequence

resets the device to reading array data.

All addresses are latched on the rising edge of AVD#.

All data is latched on the rising edge of WE#. Refer to

the AC Characteristics section for timing diagrams.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data in asynchronous mode. Each bank is

ready to read array data after completing an Embedded

Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command,

the correspond ing ba nk en ters the erase-sus-

pend-read mode, after which the system can read data

from any non-erase-suspended sector within the same

bank. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data with the same exception. See the Erase

Suspend/Erase Resume Commands section for more

information.

The system

must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase operation,

or if the bank is in the autoselect mode. See the next

section, Reset Command, for more information.

Se e a lso R equ ir emen ts f o r Asynchr o n ous

Read Operation (Non-Burst) and Requirements for

Synchronous (Burst) Read Operation in the Device

Bus Operations section for more information. The

Asynchronous Read and Synchronous/Burst Read

tables provide the read parameters, and Figures 9 and

11 show the timings.

Set Wait State Command Sequence

The wait state command sequence instructs the device

to set a particular number of clock cycles for the initial

access in burst mode. The number of wait states that

should be programmed into the device is directly

related to the clock frequency. The first two cycles of

the command sequence are for unlock purposes. On

the third cycle, the system should write C0h to the

address associated with the intended wait state setting

(see Table 3). Address bits A12 and A13 determine the

setting.

Table 3.

Third Cycle Address/Data

Upon power up, the device defaults to the maximum

seven cycle wait state setting (see Figure 20). It is rec-

ommended that the wait state command sequence be

written, even if the default wait state value is desired, to

ensure the device is set as expected. A hardware reset

will set the wait state to the default setting.

Handshaking

The host system should set the wait states to 00h for a

clock frequency of 40 MHz or to 01h for a clock fre-

quency of 54 MHz.

Enable PS (Power Saving) Mode

Command Sequence

The Enable PS (Power Saving) Mode command

sequence is required to set the device to the PS mode.

On power up, the Power Saving mode is disabled. The

command sequence consists of two unlock cycles fol-

lowed by a command cycle in which the address and

data should 555h/70h, respectively. The PS mode

remains enabled until the device is hardware reset

(either device is powered down or RESET# is asserted

low).

Sector Lock/Unlock Command Sequence

The sector lock/unlock command sequence allows the

system to determine which sectors are protected from

accidental writes. When the device is first powered up,

all sectors are locked. To unlock a sector, the system

must write the sector lock/unlock command sequence.

Two cycles are first written: addresses are don’t care

and data is 60h. During the third cycle, the sector

address (SLA) and unlock command (60h) is written,

while specifying with address A6 whether that sector

should be locked (A6 = VIL) or unlocked (A6 = VIH).

After the third cycle, the system can continue to lock or

unlock additional cycles, or exit the sequence by writing

F0h (reset command).

Note that the last two outermost boot sectors can be

locked by taking the WP# signal to VIL. Also, if VPP is at

VIL all sectors are locked; if the VPP input is at VPP, all

sectors are unlocked.

Address

A13

A12

Total Initial

Access

Cycles

Data

000555h

C0h

001555h

002555h

003555h

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