AM29BDS643D datasheet(10/46 Pages) AMD

10 / 46 page

Am29BDS643D

PRELI M INARY

after the rising edge of each successive clock cycle,

which automatically increments the internal address

counter. Note that the device has a fixed internal

address boundary that occurs every 64 words,

starting at address 00003Eh. The transition from

the highest address 3FFFFFh to 000000h is also a

boundary crossing. During the time the device is out-

putting the 64th word (address 00003Eh, 00007Eh,

0000BEh, etc.), a two cycle latency occurs before data

appears for the next address (address 00003Fh,

00007Fh, 0000BFh, etc.). The RDY output indicates

this condition to the system by pulsing low. See Figures

18 and 19.

The device will continue to output sequential burst

data, wrapping around to address 000000h after it

reaches the highest addressable memory location,

until the system asserts CE# high, RESET# low, or

AVD# low in conjunction with a new address. See Table

1. The reset command does

not terminate the burst

read operation.

If the host system crosses the bank boundary while

reading in burst mode, and the device is not program-

ming or erasing, a two-cycle latency will occur as

described above. If the host system crosses the bank

boundary while the device is programming or erasing,

the device will provide asynchronous read status infor-

mation. The clock will be ignored. After the host has

completed status reads, or the device has completed

the program or erase operation, the host can restart a

burst operation using a new address and AVD# pulse.

If the clock frequency is less than 6 MHz during a burst

mode operation, additional latencies will occur. RDY

indicates the length of the latency by pulsing low.

Programmable Wait State

The programmable wait state feature indicates to the

device the number of additional clock cycles that must

elapse after AVD# is driven active before data will be

available. Upon power up, the device defaults to the

maximum of seven total cycles. The total number of

wait states is programmable from four to seven cycles.

See Figure 20.

Handshaking

The handshaking feature allows the host system to

simply monitor the RDY signal from the device to deter-

mine when the initial word of burst data is ready to be

read. The host system should use the wait state

command sequence to set the number of wait states for

optimal burst mode operation (00h for 40 MHz clock

and 01h for 54 MHz clock. The initial word of burst data

is indicated by the rising edge of RDY after OE# goes

low.

The presence of the handshaking feature may be veri-

fied by writing the autoselect command sequence to

the device. See “Autoselect Command Sequence” for

details.

Power Saving Function

The Power Save function reduces the amount of

switching on the data output bus by changing the

minimum number of bits possible, thereby reducing

power consumption. This function is active only during

burst mode operations.

The device compares the word previously output to the

system with the new word to be output. If the number of

bits to be switched is 0–8 (less than half the bus width),

the device simply outputs the new word on the data

bus. If, however, the number of bits that must be

switched is 9 or higher, the data is

inverted before being

output on the data bus. This effectively limits the

maximum number of bits that are switched for any

given read cycle to eight. The device indicates to the

system whether or not the data is inverted via the PS

(power saving) output. If the word on the data bus is

not

inverted, PS = VIL; if the word on the data bus is

inverted, PS = VIH.

During initial power up the PS function is disabled. To

enable the PS function, the system must write the

Enable PS command sequence to the flash device (see

the Command Definitions table).

When the PS function is enabled, one additional clock

cycle is inserted during the initial and second access of

a burst sequence. See Figure 19. The RDY output indi-

cates this condition to the system.

The device is also capable of receiving inverted data

during program operations. The host system must indi-

cate to the device via the PS input whether or not the

program data is inverted. PS must be driven to VIH for

inverted data, or to VIL for non-inverted data.

To disable the PS function, the system must hardware

reset the device (drive the RESET# input low).

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 21 shows how read and write cycles

may be initiated for simultaneous operation with zero

latency. Refer to the DC Characteristics table for

read-while-program and read-while-erase current

specifications.

Writing Commands/Command Sequences

The device has inputs/outputs that accept both ad-

dress and data information. To write a command or

command sequence (which includes programming

data to the device and erasing sectors of memory), the

system must drive CLK, AVD# and CE# to VIL, and

OE# to VIH when providing an address to the device,

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