STM8S datasheet(136/467 Pages) STMICROELECTRONICS

136 / 467 page

Timer overview

RM0016

136/467

DocID14587 Rev 14

16.2

Glossary of timer signal names

Table 35. Glossary of internal timer signals

Internal signal name

Description

Related figures

Break interrupt

Figure 31: TIM1 general block diagram on

page 140

CCiI: CC1I, CC2I, CC3I, CC4I

Capture/compare

interrupt

CK_CNT

Counter clock

Figure 35: Counter update when ARPE =

0 (ARR not preloaded) with prescaler = 2

on page 144

CK_PSC

Prescaler clock

CNT_EN

Counter enable

CNT_INIT

Counter initialize

Figure 45: TI2 external clock connection

example on page 152

ETR

External trigger from

TIMx_ETR pin

Figure 47: External trigger input block

diagram on page 154

ETRF

External trigger filtered

ETRP

External trigger

prescaled

fMASTER

Timer peripheral clock

from clock controller

(CLK)

Figure 20: Clock tree and Figure 12:

Clock structure on page 61

ICi : IC1, IC2

Input capture

Figure 64: Input stage of TIM 1 channel 1

on page 168

ICiPS: IC1PS, IC2PS

Input capture prescaled

MATCH1

Compare match

Figure 54: Trigger/master mode selection

blocks on page 161 and Section 17.7.2:

Control register 2 (TIM1_CR2) on

page 190

OCi: OC1, OC2

Timer output channel

Figure 68: Detailed output stage of

channel with complementary output

(channel 1) on page 172

OCiREF: OC1REF, OC2REF

Output compare

reference signal

TGI

Trigger interrupt

Figure 43: Clock/trigger controller block

diagram on page 151

TIi : TI1, TI2

Timer input

Figure 64: Input stage of TIM 1 channel 1

on page 168

TIiF: TI1F, TI2F

Timer input filtered

TI1_ED

Timer input edge

detector

TIiFPn: TI1FP1, TI1FP2,

TI2FP1, TI2FP2, TI3FP3,

TI3FP4, TI4FP3, TI4FP4

Timer input filtered

prescaled

TRC

Trigger capture

TRGI

Trigger input to

clock/trigger/slave

mode controller

Figure 44: Control circuit in normal mode,

fCK_PSC = fMASTER on page 152

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