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RM0016

Universal asynchronous receiver transmitter (UART)

377

22.3.9

UART synchronous communication

The UART transmitter allows the user to control bidirectional synchronous serial

communications in master mode.

In synchronous mode, the following bits must be kept cleared:

•

LINEN bit in the UART_CR3 register

•

SCEN, HDSEL and IREN bits in the UART_CR5 register

Note:

This feature is only available in UART1, UART2 and UART4.

The UART_CK pin is the output of the UART transmitter clock. No clock pulses are sent to

the UART_CK pin during start bit and stop bit. Depending on the state of the LBCL bit in the

UART_CR3 register clock pulses will or will not be generated during the last valid data bit

(address mark). The CPOL bit in the UART_CR3 register allows the user to select the clock

polarity, and the CPHA bit in the UART_CR3 register allows the user to select the phase of

the external clock (see Figure 122, Figure 123 & Figure 124).

During idle and break frames, the external CK clock is not activated.

In synchronous mode, the UART receiver works differently compared to asynchronous

mode. If RE=1, the data is sampled on SCLK (rising or falling edge, depending on CPOL

and CPHA), without any oversampling. A setup and a hold time (even if the hold time is not

relevant due to the SPI protocol) must be respected (which depends on the baud rate: 1/16

bit time for an integer baud rate).

Note:

The UART_CK pin works in conjunction with the TX pin. When the UART transmitter is

disabled (TEN and REN= 0), the UART_CK and UART_TX pins go into high impedance

state.

The LBCL, CPOL and CPHA bits in UART_CR3 have to be selected when both the

transmitter and the receiver are disabled (TEN=REN=0) to ensure that the clock pulses

function correctly. These bits should not be changed while the transmitter or the receiver is

enabled.

It is recommended to set TE and RE are set in the same instruction in order to minimize the

setup and the hold time of the receiver.

The UART supports master mode only: it cannot receive or send data related to an input

clock (SCLK is always an output).

The data given in this section apply only when the UART_DIV[3:0] bits in the UART_BRR2

bit time.

This option allows to serially control peripherals which consist of shift registers, without

losing any functions of the asynchronous communication which can still talk to other

asynchronous transmitters and receivers.

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