AD9546SLASHPCBZ datasheet(143/205 Pages) AD

143 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 143 of 205

CAVEATS OF CASCADED DPLL OPERATION

The recommendation is to avoid using reference synchronization

when employing cascaded DPLL operation (see the Reference

Synchronization section).

When the profile targeted by the assigned inactive profile index

becomes inactive, certain aspects of the target profile

configuration still matter (even though the target profile is

inactive), as follows:

•

The translation type (phase buildout or hitless—see the

Translation Modes section). For phase buildout mode, the

APLL associated with the primary DPLL must be in a

calibrated and locked state. For hitless (internal) mode, the

APLL associated with the primary DPLL must be in a

calibrated and locked state, and the selected distribution

path must be active (that is, a synchronization event has

occurred (see the Distribution Output Clock

Synchronization section) on the channel associated with

the secondary DPLL).

•

The device uses the information related to the feedback

configuration of the primary DPLL (even though the

primary DPLL is effectively operating open loop, that is,

holdover or freerun).

•

The user cannot specify fractional feedback division for the

primary DPLL (that is, the device ignores the fractional

portion of the feedback divider when operating in the

cascaded DPLL configuration). Furthermore, the user

must properly program the buildout N divider value in the

targeted inactive profile (even if the targeted inactive

profile is a hitless (internal) profile). See the DPLL

Feedback Divider (N Divider) section for details relating to

the buildout N divider.

•

The user cannot specify the external zero delay configuration

for cascaded DPLL operation.

•

The device uses the information related to time stamp

tagging according to the primary DPLL. Specifically, the

tagging mode defined for the feedback path of the primary

DPLL determines whether time stamp tags are available on

the reference input path of the secondary DPLL. Thus, the

targeted inactive profile for the primary DPLL must use a

value of 2, 3, or 4 as the tag mode. In addition, the translation

profile for the secondary DPLL must use a value of 1, 3, or 4

as the tag mode (see Table 86 regarding the tag modes).

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