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AD9546/PCBZ データシート(PDF) 141 Page - Analog Devices |
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AD9546/PCBZ データシート(HTML) 141 Page - Analog Devices |
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141 / 205 page  Data Sheet AD9546 Rev. 0 | Page 141 of 205 CASCADED DPLL CONFIGURATION The cascaded DPLL configuration applies to applications that lock both DPLLs to the same reference source with both DPLLs remaining phase locked, even if all reference sources are lost. To understand cascaded configurations, first consider device operation without cascaded capability, as shown in Figure 98. As a prerequisite, the reader must be familiar with the Translation Profiles section and the Reference Switching section. Figure 98 and Figure 99 show simplistic diagrams of the DPLL showing a phase buildout configuration, but the zero delay (hitless) configuration is valid as well. The far left side of Figure 98 shows two valid reference sources with DPLL0 and DPLL1 using Translation Profile 0.a and Translation Profile 1.z, respectively, assigned to Reference Source 1, where a and z are variables that can be any integer value from 0 to 5. Therefore, both DPLLs lock to a common reference as desired. The middle portion of Figure 98 shows the result of losing Reference Source 1. The loss of Reference Source 1 results in both DPLLs independently searching for a new reference source, assuming automatic reference switching is in effect (see the Reference Switching section). Presumably, the user has defined translation profiles in such a way that DPLL0 finds Translation Profile 0.b and DPLL1 finds Translation Profile 1.y (where b and y are variables that can be any integer value from 0 to 5, but not the same value as the a and z variables) with both profiles assigning the same valid reference source (Reference Source 2, in this example). As such, both DPLLs again lock to a common reference as desired. The far right hand side of Figure 98 shows the result of losing Reference Source 2, leaving no valid reference sources. In this case, both DPLLs have no recourse but to switch to holdover or freerun mode. However, because the DPLLs may not have the same FTW in effect when they switch to holdover or freerun mode, their outputs are no longer phase locked, which breaks the original requirement that both DPLLs remain phase locked when all reference sources are lost. The cascaded configuration provides a solution to this problem. DIGITAL CROSS POINT MUX TDC 2 REFERENCE SOURCES TO APLL0 PFD LF NCO N DPLL0 PFD LF NCO N DPLL1 TO APLL1 REFERENCE SOURCE 1 LOST TO APLL0 NCO NCO TO APLL1 FTW FTW TRANSLATION PROFILE 0.a TRANSLATION PROFILE 1.z TO APLL0 PFD LF NCO N DPLL0 PFD LF NCO N DPLL1 DPLL0 DPLL1 TO APLL1 TRANSLATION PROFILE0.b TRANSLATION PROFILE 1.y ALL REFERENCE SOURCES LOST DIGITAL CROSS POINT MUX DIGITAL CROSS POINT MUX BOTH DPLLS SWITCH TO HOLDOVER/FREERUN TRANSLATION PROFILE 0.a AND TRANSLATION PROFILE 1.z ASSIGN REFERENCE SOURCE 1 TRANSLATION PROFILE 0.b AND TRANSLATION PROFILE 1.y ASSIGN REFERENCE SOURCE 2 TDC 2 REFERENCE SOURCES TDC 1 Figure 98. Noncascaded DPLL Operation |
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