AD9546SLASHPCBZ datasheet(139/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 139 of 205

Delay Compensation Coefficients (Ck) Programming

Coefficient Ck (where k = 1 to 5) applies scale factors to the

appropriate powers of T. The Ck coefficients carry units of

sec/°C. Each coefficient comprises a significand component and

an exponent component. The user programs the significand

and exponent components independently in the register map.

The coefficient components reside in the register map per

Table 84.

Table 84. Delay Compensation Coefficient Address Ranges

DPLL

Coefficient

Significand

Exponent

0x101A to 0x101B

0x101C

0x101D to 0x101E

0x101F

0x1020 to 0x1021

0x1022

0x1023 to 0x1024

0x1025

0x1026 to 0x1027

0x1028

0x141A to 0x141B

0x141C

0x141D to 0x141E

0x141F

0x1420 to 0x1421

0x1422

0x1423 to 0x1424

0x1425

0x1426 to 0x1427

0x1428

The significand and exponent values are signed (twos

complement) numbers and program in exactly the same manner

as the significand and exponent of the Tk values for system

clock compensation (see the Compensation Method 1 section

for details on converting decimal coefficient values to signed,

twos complement, significand and exponent values).

For example, suppose a user makes measurements that indicate

the output clock signals of the AD9546 exhibit a delay variation

of −1 ns/°C. To compensate for this variation, apply a 1 ns/°C

correction. In polynomial form,

f(T) = C5

T5 + C4T4 + C3T3 + C2T2 + C1T

where f(T) is the correction value in units of seconds as a

function of temperature (T).

Because the delay variation in this example is strictly linear with

respect to temperature, all the coefficients are zero except for

C1. Thus, in this example, the compensation polynomial

simplifies to the following:

f(T) = C1

To apply 1 ns/°C compensation, C1 = 10−9 sec/°C. Referring to

the procedure in the Compensation Method 1 section, calculate

the following for C1:

C1_ExpVal =

log













log

-9













= −29

Because −29 is greater than the quantization limit of −127, the

C1 exponent is

C1 Exponent = C1_ExpVal

= −29

= 0xE3 (hexadecimal)

The C1 significand is

C1 Significand = C1 × 215 − C1_ExpVal

= 10−9 × 215 − (−29)

= 17,592 (nearest integer)

= 0x44B8 (hexadecimal)

Delay Compensation Filter

The Δt values produced by the delay compensation block depend

on temperature measurements (internal or via the register map)

as an input parameter. Any noise associated with those

measurements is a potential noise source on Δt, which can lead

to a degradation of the phase noise performance of the DPLL.

To mitigate potential noise injection, the delay compensation

block uses a filter that applies a smoothing function to the raw

Δt values.

The phase slew limiter (see the Phase Slew Rate Limit section)

does not process time variations injected into the DPLL by the

delay compensation filter. That is, these variations affect the

DPLL output without intervention by the phase slew limiter.

The user controls the filter bandwidth via Bits[2:0] (unsigned)

of Register 0x1029 (for DPLL0) and Register 0x1429 (for

DPLL1). The filter comprises a single-pole response yielding a 3

dB bandwidth per Table 85 (which also shows the transition

time to 99% of a step input, associated with a step change at the

input to the filter).

Table 85. Delay Compensation Filter Bandwidth

Bits[2:0]

3 dB Bandwidth (Hz)

Transition Time (ms)

000

240

3.27

001

120

6.58

010

13.0

011

26.5

100

53.1

101

7.6

99.5

110

3.8

199

111

1.9

398

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