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AD9546/PCBZ データシート(PDF) 149 Page - Analog Devices

部品番号 AD9546/PCBZ
部品情報  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD9546/PCBZ データシート(HTML) 149 Page - Analog Devices

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Data Sheet
AD9546
Rev. 0 | Page 149 of 205
Active Profile
When the DPLL selects a specific translation profile, whether
manually or automatically, the selected profile becomes active.
When a translation profile is active, the corresponding bit is
Logic 1 in Register 0x3009 (DPLL0) or Register 0x300A
(DPLL1). Bits[5:0] associate with Translation Profile x.5
through Translation Profile x.0, respectively, where x = 0 or 1.
The IRQ status section of the register map indicates Logic 0 to
Logic 1 transitions of Bits[5:0] of Register 0x3013 (DPLL0) and
Register 0x3018 (DPLL1). Because the IRQ bits are latched bits,
the user must clear them via Bits[5:0] of Register 0x200E (DPLL0)
and Register 0x2013 (DPLL1) to obtain visibility of subsequent
Logic 0 to Logic 1 transitions of Bits[5:0] in Register 0x3009
(DPLL0) and Register 0x300A (DPLL1) (see the Interrupt
Request (IRQ) section).
An active translation profile is not the same as a valid translation
profile. That is, a profile can be valid without being active.
When all translation profiles for a particular DPLL are inactive, the
user can find the most recently active profile via Bits[6:4] of
Register 0x3101 (DPLL0) and Register 0x3201 (DPLL1). The
value of Bits[6:4] corresponds to the most recently active
profile. If a translation profile is currently active (as indicated
by Bits[5:0] in Register 0x3009 and Register 0x300A), the value
of Bits[6:4] in Register 0x3101 (DPLL0) and Register 0x3201
(DPLL1) identify the currently active profile.



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