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AD9546/PCBZ データシート(PDF) 150 Page - Analog Devices

部品番号 AD9546/PCBZ
部品情報  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9546/PCBZ データシート(HTML) 150 Page - Analog Devices

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AD9546
Data Sheet
Rev. 0 | Page 150 of 205
START
YES
NO
YES
NO
YES
NO
= 0?
= 1?
REG 0x2105,
BIT 1
= 1?
SELECT TRANSLATION
PROFILE 0.x PER
AUTOMATIC,
PRIORITY-BASED
TRANSLATION
PROFILE SELECTION
MANUAL ONLY
TRANSLATION
PROFILE
SELECTION1
YES
NO
= 3?
YES
= 2?
MANUAL
TRANSLATION
PROFILE
SELECTION
WITH FALLBACK
TO HOLDOVER
DPLL USES
DPLL USES
TRANSLATION
PROFILE 0.x
DPLL USES SELECTED
TRANSLATION PROFILE
MANUAL TRANSLATION PROFILE
SELECTION WITH FALLBACK TO
PRIORITY- BASED TRANSLATION
PROFILE SELECTION
FORCED
FREERUN
1FOR DEBUG ONLY. THE DPLL USES TRANSLATION PROFILE 0.x WITHOUT VALIDATING THE SOURCE. THEREFORE, THE DPLL
IS NOT GUARANTEED TO FUNCTION NORMALLY. CONTACT ANALOG DEVICES FOR DETAILS.
ENTER
EXIT
HOLDOVER
PROCEDURE
PRIORITY
SELECTION
PROCEDURE
YES
NO
PASS?
ENTER
EXIT
TRANSLATION
PROFILE
VALIDATION
PROCEDURE
YES
NO
PROFILE
VALID?
NO
REG 0x2105, BITS[3:2] = 1
FORCED
HOLDOVER
NOTES
1. A RANGE OF BITS USES A COLON SEPARATOR
2. REGISTER ADDRESSES ARE SPECIFIC TO DPLL0
REG 0x2105,
BIT 0
REG 0x2105,
BITS[3:2]
REG 0x2105, BITS[6:4]
REG 0x2105,
BITS[3:2]
REG 0x2105,
BITS[3:2]
REG 0x1005 TO 0x1000,
BITS[45:0]
Figure 102. DPLL Mode Selection Flowchart



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