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AD9546/PCBZ データシート(PDF) 152 Page - Analog Devices

部品番号 AD9546/PCBZ
部品情報  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9546/PCBZ データシート(HTML) 152 Page - Analog Devices

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AD9546
Data Sheet
Rev. 0 | Page 152 of 205
TRANSLATION PROFILE
VALIDATION PROCEDURE
YES
NO
REG 0x3001,
BIT 1
= 1?
TRANSLATION
PROFILE 0.2
ENABLED?
NO
REG 0x1240,
BIT 0
= 1?
REG 0x3100,
BIT 5
= 1?
REG 0x3020,
BIT 4
= 1?
REG 0x3201,
BIT 0
= 1?
REG 0x1243,
BIT 0
= 0?
REG 0x1243,
BIT 1
= 0?
REG 0x3100,
BIT 3
REG 0x1241,
BITS[4:0]
= 1?
SYSTEM CLOCK
STABLE?
VALID
INVALID
APLL0
CALIBRATED?
NO
APLL0
LOCKED?
NO
REFA, REFAA,
REFB, REFBB,
Aux REF0, REF1,
REF2, REF3
OR IUTS0/IUTS1?
NO
0 TO 3,6,7,
11 TO 14?
=
REG 0x1241,
BITS[4:0]
REG 0x1241,
BITS[4:0]
8 OR 9?
=
AUX NCO
0 OR 1?
NO
DPLL1
FEEDBACK?
NO
= 5?
DPLL1
FREERUN?
NO
DPLL1
HOLDOVER?
NO
APLL1
CALIBRATED?
NO
APLL1
LOCKED?
NO
YES
YES
YES
YES
YES
YES
YES
YES
YES
AUX REF1
VALID?
NO
YES
REFERENCE SOURCE VALIDATION
EXAMPLE
EXAMPLE
NO
YES
TRANSLATION
PROFILE 0.2
BUILDOUT
EXAMPLE
NO
YES
TRANSLATION PROFILE
0.2 HITLESS
EXAMPLE
YES
YES
NO
TRANSLATION PROFILE 0.2
EXTERNAL ZERO DELAY
NO
NO
EXAMPLE
TRANSLATION PROFILE 0.2
INTERNAL ZERO DELAY
EXAMPLE
ENTER
EXIT
0.2
DISTRIBUTION
FEEDBACK PATH
SYNCED (OR SYNC REQUEST
AWAITING TRIGGER)?
DISTRIBUTION
FEEDBACK CHANNEL NOT
POWERED DOWN?
YES
EXTERNAL
ZERO DELAY
REFERENCE SOURCE
VALID?
NOTES
1. A RANGE OF ADDRESSES OR BITS USES A COLON SEPARATOR
2. REGISTER ADDRESSES ARE SPECIFIC TO DPLL0, TRANSLATION PROFILE 0.2 (EXAMPLE), AND AUXILIARY REF1 (EXAMPLE)
REG 0x3201,
BIT 1
= 1?
REG 0x3200,
BIT 5
= 1?
REG 0x3200,
BIT 3
= 1?
YES
Figure 104. Flowchart for Translation Profile Validation



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