AD9546SLASHPCBZ datasheet(154/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 154 of 205

TIME TO DIGITAL CONVERTER (TDC)

TDCs are at the core of the DPLL technology in the AD9546.

The purpose of a TDC is to continuously observe a clock signal,

note the occurrence of an edge transition, and generate a digital

time stamp identifying when the edge occurred.

Because a TDC effectively digitizes rising edge clock events by

means of time stamps, it enables digital (that is, numeric)

processing of clock signals. In a conventional PLL, for example,

a PFD circuit measures the relative phase of the reference and

feedback signals and provides an analog representation of the

phase difference. Instead of an analog representation of the

phase difference, the AD9546 uses a pair of TDCs (one in the

reference path and one in the feedback path) to generate

reference and feedback time stamps, constituting a numeric

representation of the phase difference. With phase information

in numeric form, the AD9546 implements the entire PLL

function digitally by employing a numeric PFD, digital loop

filter and an NCO.

Figure 106 shows a simplified diagram of a TDC. The TDC has

a time base clock (which gives the TDC its sense of time), an

input clock (the signal in question), and an output consisting of

numeric time stamps.

TIME STAMPS

ONE PER INPUT

CLOCK EDGE EVENT

TIME BASE CLOCK

INPUT CLOCK

TDC

Figure 106. TDC Diagram

The AD9546 contains 10 TDCs.

•

Four at the output of the reference dividers associated with

the four reference inputs

•

Four at the output of the reference dividers associated with

the auxiliary reference inputs

•

Two associated with the two DPLLs at the output of the

feedback divider

Each TDC produces digital time stamps identifying each rising

edge of its input clock. That is, the TDCs generate time stamps

at a rate commensurate with their respective input clock period.

The user must, however, ensure the TDC input clock rate is

within the specified range of 1 Hz to approximately 200 kHz.

The TDC time stamps derive from an internal time base that

originates with the device system clock. As such, the TDCs

benefit from the ability of the AD9546 to provide system clock

compensation, assuming the user activates system clock

compensation via Register 0x0280 to Register 0x0282 (see the

System Clock Compensation section).

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