SAMA5D2 datasheet(5/56 Pages) MICROCHIP

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– One USB high-speed device port (UDPHS) and one USB high-speed host port or two USB high-speed host

ports (UHPHS)

– One USB high-speed host port with a High-Speed Inter-Chip (HSIC) interface

– One 10/100 Ethernet MAC (GMAC)

• Energy efficiency support (IEEE 802.3az standard)

• Ethernet AVB support with IEEE802.1AS time stamping

• IEEE®802.1Qav credit-based traffic-shaping hardware support

• IEEE1588 Precision Time Protocol (PTP)

– Two high-speed memory card hosts:

• SDMMC0: SD 3.0, eMMC 4.51, 8 bits

• SDMMC1: SD 2.0, eMMC 4.41, 4 bits only

– Two host/client Serial Peripheral Interfaces (SPI)

– Two Quad Serial Peripheral Interfaces (QSPI)

– Five FLEXCOMs (USART, SPI and TWI)

– Five UARTs

– Two host CAN-FD (MCAN) controllers with SRAM-based mailboxes, and time- and event-triggered

transmission

WARNING

MCAN implements the non-ISO CAN FD frame format and therefore does not pass the CAN FD

Conformance Test according to ISO 16845-1:2016.

– One Rx only UART in backup area (RXLP)

– One analog comparator (ACC) in backup area

– Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I2C protocol and SMBUS (TWIHS)

– Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes

– One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller

– One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with Resistive TouchScreen capability

• Safety

– Zero-power Power-On Reset (POR) cells

– Main crystal clock failure detector

– Write-protected registers

– Integrity Check Monitor (ICM) based on SHA256

– Memory Management Unit

– Independent watchdog

• Security

– 5 Kbytes of internal scrambled SRAM:

• 1 Kbyte non-erasable on tamper detection

• 4 Kbytes erasable on tamper detection

– 256 bits of scrambled and erasable registers

– Up to eight tamper pins for static or dynamic intrusion detections(1)

– Environmental monitors on specific versions: temperature, voltage, frequency and active die shield(2)

– Secure Boot Loader(3)

– On-the-fly AES encryption/decryption on LPDDR2/DDR2-SDRAM and QSPI memories (AESB)

– RTC including time-stamping on security intrusions

– Programmable fuse box with 544 fuse bits (including JTAG protection and BMS)

• Hardware Cryptography

– SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2

– AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197

– TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3

SAMA5D2 SIP

Features

Datasheet

DS60001484D-page 5

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