SPSB0813 datasheet(57/135 Pages) STMICROELECTRONICS

57 / 135 page

Symbol

Parameter

Condition

Min Typ Max Unit Item

tV1FS

V1 fail-safe filter time

Tested by scan

1.43

2.06

ms C.019

tV1off

V1 deactivation time after 8

consecutive WD failures

Tested by scan

200

270

ms C.020

1. Below 3.55 V, the POR VSREG can be activated and there is a device reset.

2. Guaranteed by design.

3. Nominal capacitor value required for stability of the regulator. Tested with 1 μF ceramic (+/- 20%). Capacitor must be located

close to the regulator output pin. A 2.2 uF capacitor value is recommended to minimize the DPI (Direct power injection)

stress in the application.

4. In active mode, V1 regulator is switched to high accuracy mode. Below the Icmp threshold, regulator switches in any case to

nominal accuracy mode (same behavior applies also in case of high current).

5.4

Voltage regulator V2

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V

< VS< 28 V; 4.5 V < VSREG< 28 V; Tj = from -40°C to 150°C, unless otherwise specified.

The same parameter values in both 5 V and 3.3 V conditions apply unless otherwise specified.

Table 31. Voltage regulator V2

Symbol

Parameter

Condition

Min Typ Max Unit Item

Output voltage including line

and load regulation

VSREG ≥ 6.5 V

5.0

C.053

3.3

C.054

V2high_acc

Output voltage tolerance

High accuracy mode

ILOAD = 100 μA to 50mA, (active mode)

VSREG = 13.5 V

-2.5

+2.5

C.055

V2100mA

Output voltage tolerance (50 …

100mA)

ILOAD = 100 mA,

VSREG = 13.5 V

-3

C.056

ΔVo

(1)

Output voltage tracking accuracy

Icc2 = 100 µA to 100 mA, Icc1=30 mA Vsreg

= 6.5 V to 28 V

-20

mV C.057

VDP2

Drop-out voltage

Iload =30 mA; VSREG =5.25 V (V2=5V) and

VSREG =3.55 V (V2=3.3 V)

0.3

0.5

C.022

Iload =100 mA @ T= 25°C;

VSREG =5.0 V (V2 = 5.0 V) and

VSREG = 3.55 V (V2 = 3.3 V)

0.75 0.85

C.058

ICCmax2

Output current limitation

400 600 1200 mA C.023

Cload(2)(3)

Load capacitor

Ceramic (+/- 20%)

μF

C.024

V2fail_5

V2 short circuit voltage to switch

V2 off and set SPI bit

V2 forced (V2 = 5 V)

C.025

V2fail_33

V2 forced (V2 = 3V3)

1.3

C.060

tV2fail

V2 fail filter time

Tested by scan

µs

C.068

tV2short

V2 short filter time

Tested by scan

ms C.026

1. Output voltage tracking accuracy are guaranteed only in DC condition.

2. Nominal capacitor value required for stability of the regulator. Tested with 1µF ceramic (+/- 20%). Capacitor must be located

close to the regulator output pin. A 2.2 μF capacitor value is recommended to minimize the DPI stress in the application.

3. Guaranteed by design.

5.5

Reset output

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 4 V ≤

VS ≤ 28 V; 4 V < VSREG< 28 V; Tj = from -40 to 150°C, unless otherwise specified.

SPSB081

Voltage regulator V2

DS14048 - Rev 1

page 57/135

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