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SPSB0813 データシート(PDF) 77 Page - STMicroelectronics |
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SPSB0813 データシート(HTML) 77 Page - STMicroelectronics |
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77 / 135 page  Symbol Parameter Condition Min Typ Max Unit Item tdis DO L tri (1) DO disable time from low level to 3- state CL = 50 pF, Iload = 4 mA pull-up load to V1 50 100 ns B.029 ten DO tri H (1) DO enable time from tristate to high level CL = 50 pF, Iload = -1 mA pull-down load to GND 50 100 ns B.030 td DO (1) DO delay time VDO < 0.3 V1 or VDO > 0.7 V1, CL = 50 pF 25 30 ns B.031 1. Guaranteed by design. Table 60. CSN timing Symbol Parameter Condition Min Typ Max Unit Item tCSN_HI,min Minimum CSN HI time, active mode Transfer of SPI-command to input register 0.5 μs B.032 tCSNfail (1) CSN low timeout 20 35 50 ms B.033 1. Guaranteed by design. Figure 35. SPI – transfer timing diagram The SPI can be driven by a microcontroller with its SPI peripheral running in the following mode: CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. SPSB081 SPI DS14048 - Rev 1 page 77/135 |
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