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SPSB0813 データシート(PDF) 85 Page - STMicroelectronics |
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SPSB0813 データシート(HTML) 85 Page - STMicroelectronics |
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85 / 135 page  Bit Name Description • CAN_PERM_REC • CAN_PERM_DOM • CAN_TXD_DOM 0 = no error (default) 1 = error detected PLE is cleared by a read & clear command to all related bits in status registers 2. 27 FE Functional error bit The FE is a logical OR combination of errors coming from functional blocks. SR2 (0x32): • V2SC SR3 (0x33): • OUTx OC SR4 (0x34):(3) • OUTx OL 0 = no error (default) 1 = error detected FE is cleared by a read & clear command to all related bits in status registers 2, 3, 4 26 DE Device error bit DE is a logical OR combination of global errors related to the device. SR1 (0x31): • TSD1 SR2 (0x32): • VS_OV • VS_UV • VSREG_OV • VSREG_UV • V1_OV 0 = no error (default) 1 = error detected DE is cleared by a read & clear command to all related bits in status registers 2 25 GW (2) Global warning bit GW is a logical OR combination of warning flags. Warning bits do not lead to any device state change or switch off of functions. SR2 (0x32): • V1FAIL • V2FAIL • CAN_RXD_REC • TW (3) • SPI_INV_CMD • SPI SCK CNT SR6 (0x36): • CAN_SUP_LOW 0 = no error (default) 1 = error detected GW is cleared by a read & clear command to all related bits in status register 2. 24 FS Failsafe The FS bit indicates that the device was forced into a safe state due to the following failure conditions: SR1 (0x31): • WDFAIL SPSB081 Global status byte (GSB) DS14048 - Rev 1 page 85/135 |
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