 |
データシートサーチシステム |
|
|
データシートサーチシステム |
|
SPSB0813 データシート(PDF) 96 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPSB0813 データシート(HTML) 96 Page - STMicroelectronics |
|
|
96 / 135 page  Bit Name Description 1 TSW2 Writing to WD_TIME is blocked unless WD CONFIG EN = 1. The modified WD Trigger Time is valid only after the next trig event. Before it, old TSW value is kept. 3 V2_TKR Voltage Regulator V2 configurable as a linear independent LDO or a tracker of the V1 Voltage Regulator 0 Linear independent LDO (default) 1 Tracker of the V1 voltage regulator 2 V2_RAIL Voltage Regulator V2 rail configuration 0 V2 = 3.3V (default) 1 V2 = 5V 1 STBY SEL Following are the valid settings: 1 1 : go to V1 standby 1 0 : No transition to standby 0 1 : Go to VBAT_standby 0 0 : No transition to standby (default) 0 GO STBY 1. When the configuration of a timer is changed, the timer is automatically restarted using the new configuration. Table 75. Control register CR3 (0x03) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name Access 1 (R/W) 0 (R) 1 (R/W) 0 (R) 0 (R) SPSB081 Control registers DS14048 - Rev 1 page 96/135 |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか？ [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
