L9945 datasheet(36/151 Pages) STMICROELECTRONICS

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Table 22. tOFF selection

HBx_toff [1-0]

Min tOFF value

Typical tOFF value

Max tOFF value

Unit

µs

62.5

µs

110

125

140

µs

5.5.7

H-Bridge OFF state diagnostic timings

The device offers the possibility to select the OFF state diagnostic filter times tDIAG among two different strategies,

selectable via HBx_tdiag_ext_config bit (refer to Table 23):

•

When HBx_tdiag_ext_config = 0, the diagnostic filter time tDIAG selected for CH1 (CH5) is automatically

extended to all channels member of the bridge;

•

When HBx_tdiag_ext_config = 1, the diagnostic filter time tDIAG must be set individually for each channel

member of the bridge.

Regardless of the strategy selected, the tDIAG filter time can be programmed via tdiag_config_xx bit.

Table 23. OFF state diagnostic timings for H-Bridge

Symbol

tdiag_config_xx

Parameter

Min.

Typ.

Max.

Unit

Comment

THB_diag_1

H-Bridge Diag Time 1

11.2

12.4

µs

HBx_tdiag_ext_config = 0

(all channels set as CH1/CH5)

THB_diag_2

H-Bridge Diag Time 2

28.9

31.8

µs

THB_diag_3

H-Bridge Diag Time 3

µs

THB_diag_4

H-Bridge Diag Time 4

51.2

56.4

µs

TDIAG_HB_100

H-Bridge Diag Time 1

25.6

28.2

µs

HBx_tdiag_ext_config = 1

(channels to be set individually)

TDIAG_HB_101

H-Bridge Diag Time 2

61.2

67.4

µs

TDIAG_HB_110

H-Bridge Diag Time 3

105.6

116.2

µs

TDIAG_HB_111

H-Bridge Diag Time 4

135

150

165

µs

5.6

Peak & Hold

The pre-drivers can be configured into two independent peak & hold blocks. In this configuration Channels 1,4 are

used for Peak & Hold 1, while Channels 2,3 are used for Peak & Hold 2.

The device can handle up to two Peak & Hold branches. There are two possible configurations which can co-

exist:

•

Peak & Hold 1: it involves channels 1 (HS) and 4 (LS) and can be activated by setting PH1_config = 1;

•

Peak & Hold 2: it involves channels 2 (HS) and 3 (LS) and can be activated by setting PH2_config = 1.

Configurations above are automatically applied once the PHx_config bit is set.

The N_P_config_xx bit set the MOSFET type (NMOS, PMOS) used in the Peak & Hold high-side.

5.6.1

Peak & Hold driving mode

All channels involved in the peak & hold configuration can be driven independently either via the corresponding

NONx pin or via SPI, depending on SPI_INPUT_SEL_xx bit. An external microcontroller shall close the control

loop in order to guarantee the desired current profile in the load. The device does not feature any internal current

control capability while in peak & hold configuration.

L9945

Peak & Hold

DS12275 - Rev 8

page 36/151

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