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LT1768

BLOCK DIAGRA

Figure 2. LT1768 Block Diagram

INTRODUCTION

The current trend in desktop monitor design is to migrate

the LCD (liquid crystal display) technology used in laptops

and instruments to the popular desktop display sizes. As

LCD size increases uniform backlighting requires mul-

tiple high power lamps. In addition, the lamps must have

a dimming range and lifetime expectancy comparable to

previous generations of desktop displays. Cold cathode

fluorescent lamps (CCFLs) provide the highest available

efficiency for backlighting LCD displays. The CCFL re-

quires a high voltage supply for operation. Typically, over

1000 volts is required to initiate CCFL operation, with

sustaining voltages from 200V to 800V. A CCFL can

operate from DC, but migration effects damage the CCFL

and shorten its lifetime. To achieve maximum life CCFL

drive should be sinusoidal, contain zero DC component,

and not exceed the CCFL manufacturers minimum and

maximum operating current ratings. Low crest factor

APPLICATIONS INFORMATION

sinusoidal CCFL drive also maximizes current to light

conversion, reduces display flicker, and minimizes EMI

and RF emissions. The LT1768 high power CCFL control-

ler, with its Multimode Dimming, provides the necessary

lamp drive to enable a wide dimming range while main-

taining lamp lifetime in multiple lamp CCFL applications.

BASIC OPERATION

Referring to the circuit in Figure 1, CCFL current is con-

trolled by a DC voltage on the PROG pin of the LT1768. The

DC voltage on the PROG pin feeds the LT1768’s Multimode

Dimming block and is converted to source current into the

VC pin. As the VC pin voltage rises, the LT1768’s GATE pin

is pulse width modulated at 350kHz. The GATE pulse width

is determined on a cycle by cycle basis by the voltage on

the SENSE pin (L1’s current multiplied by SENSE resistor

R5) exceeding a predetermined voltage set by the VC pin.

IRMAX

IRMIN

1V 4V

1.25V

1.26V

SLOPE

OSC

VPWM

PWM

VREF

RMIN

RMAX

VIN

FAULT

SHDN

PROG

AGND

DI01

DIO2

GATE

SENSE

PGND

CONTROL

MODE

IVC

VCCLAMP

FAULT

MULTI-MODE

DIMMING BLOCK

PWM PERIOD

UNDERVOLTAGE

LOCKOUT

THERMAL

SHUTDOWN

VREF

(IDIO1 + IDIO2)

GAIN

IVC

IDIO2 < 125µA

IDIO1 < 125µA

BLANK

VIN

GATE

1768 BD

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