EM6620WS27 datasheet(36/56 Pages) EMMICRO

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EM6620

www.emmicroelectronic.com

12.1 LCD Control

The LCD driver has two control registers

RegLCDCntl1,2

to optimize for display contrast,

power

consumption, operation mode and bias voltage source.

LCDExtSupply: Choosing external supply (LcdExtSupply=‘1’) disables the internal LCD voltage regulator and

voltage multiplier, it also puts the bias voltage terminals VL1, VL2 and VL3 into high impedance state. External

bias levels can now be connected to the VL1, VL2 and VL3 terminals. (Resistor divider chain or others).

Another way to adapt the VL1, VL2 and VL3 levels to specific user needs is to overdrive the VL1 output

(LcdExtSupply=0) with the desired value. The internal multiplier will multiply this new VL1 level to generate the

corresponding levels VL2 and VL3. The bit LCDExtSupply is only reset by initial POR.

LCD4Mux: With this switch one selects either 3:1 or 4:1 (default) times multiplexing of the 8 segment driver

outputs. In the case of 3:1 multiplexing the COM[4] is off.

LCDOff: Disables the LCD. The voltage multiplier and regulator are switched off ( 0 current ).The segment

latch information is maintained. The VL1, VL2 and VL3 outputs are pulled to VSS.

LCDBlank: All segment outputs are turned off. The voltage multiplier and regulator remain switched on.

LcdBlank can be used with the 1Hz and Blink interrupt to let the whole display blink (software controlled).

CkTripSel1,0: Selecting the appropriate voltage multiplier frequency to optimize display contrast and power

consumption. The value to use is also depending on the selected multiplier booster capacitors (typically

100nF).

12.2 LCD addressing

The LCD driver addressing is direct using

the registers LCD_0, LCD_1, LCD_2 until

LCD_15. All LCD Segment registers are

R/W..

A total of 16 addresses are available to the

user to define the addressing of the LCD

segment latches. For each of these latches

the user may also choose the data bit to be

connected. See also section 12.3. However

only

8x4

LCD

segment

latches

are

implemented. The unused address and bit

locations are empty and can not be used as

RAM.

Figure 26. LCD addressing

4 bit R /W

LC D _10

LC D _ 9

4 bit R /W

LC D _ 8

4 bit R /W

L CD_ 7

4 b it R/W

4 bit R /W

LC D _ 6

4 bit R /W

LC D _ 5

L CD_ 4

4 b it R/W

LC D _ 3

4 bit R /W

L CD_ 2

4 b it R /W

4 bit R /W

L CD_ 1

L CD_ 0

4 bit R /W

L CD_ 1 5

LC D _ 14

4 bit R /W

LC D _13

4 b it R /W

LC D _12

4 bit R /W

L CD_ 1 1

1 6 x 4 dir e c t a d d r e s s a ble LC D la tc he s

but m a xim u m 8 x4 bits a r e R /W

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