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EM6620WS27 データシート(PDF) 33 Page - EM Microelectronic - MARIN SA

部品番号 EM6620WS27
部品情報  Ultra Low Power Microcontroller with 4x8 LCD Driver
PDF  56 Pages
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メーカー  EMMICRO [EM Microelectronic - MARIN SA]
ホームページ  http://www.emmicroelectronic.com
Logo EMMICRO - EM Microelectronic - MARIN SA

EM6620WS27 データシート(HTML) 33 Page - EM Microelectronic - MARIN SA

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EM6620
Copyright
© 2005, EM Microelectronic-Marin SA
33
www.emmicroelectronic.com
10. Supply Voltage Level Detector
The EM6620 has a built-in Supply Voltage Level Detector (SVLD), such that the CPU can compare the supply
voltage against a pre-selected value. During Sleep Mode this function is inhibited.
The CPU activates the supply voltage level
detector by writing VldStart=1 in the register
RegVldCntl. The actual measurement starts on
the next ck[9] rising edge and lasts during the
ck[9] high period (2ms at 32kHz). The busy flag
VldBusy stays high from Start set
until the
measurement is finished. The worst case time
until the result is available is 1.5 ck[9] prescaler
clock periods (32kHz -> 6ms).
During the actual measurement the device will
draw an additional 5uA of IVDD current. After
the end of the measure an interrupt request
IRQVLD is generated and the result is available
by inspection of the bit VLDResult. If the result
is read 0, then the power supply voltage was
greater than the detection level value. If read 1,
the power supply voltage was lower than the detection level value. During each read while Busy=1 the
VLDResult is not guaranteed.
10.1 SVLD Register
Table 10.1.1 register RegVldCntl
Bit
Name
Reset
R/W
Description
3
VLDResult
0
R*
VLD result flag
2
VLDStart
0
W
VLD start
2
VLDBusy
0
R
VLD busy flag
1
NoOscWD
0
R/W
No Oscillator watchdog
0
NoLogicWD
0
R/W
No logic watchdog
R*; VLDResult is not guaranteed while VLDBusy=1
The SVLD and the PB0 Input Comparator are using the same internal measurement block. Therefore
only one of the two functions can be activated at the same time.
Figure 23. SVLD Timing Diagram
VBAT =VDD
compare level
ck[9] (256Hz)
CPU starts
measure
Busy Flag
measure
1
0
Result
Read Result
SVLD >VBAT
SVLD <VBAT
CPU starts
measure



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