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MPC604EC/D データシート(PDF) 4 Page - NXP Semiconductors |
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MPC604EC/D データシート(HTML) 4 Page - NXP Semiconductors |
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4 / 32 page ![]() 4 604 Hardware Specifications Preliminary/Subject to Change without Notice 1.3.1 Clock AC Specifications Table 5 provides the clock AC timing specifications as defined in Figure 1. Figure 1 provides the SYSCLK input timing diagram. Figure 1. SYSCLK Input Timing Diagram Table 5. PowerPC 604 Microprocessor Clock AC Timing Specifications Vdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T j ≤ 105 °C Num Characteristic 100 MHz 120 MHz 133 MHz Unit Notes Min Max Min Max Min Max Frequency of operation 50 100.0 60.0 120.0 66.67 133.3 MHz 1 Frequency of VCO 180 360 180 360 180 360 MHz 2 SYSCLK frequency 16.67 66.67 20.0 66.67 22.2 66.67 MHz 3 1 SYSCLK cycle time 15.0 60.0 15.0 50.0 15.0 45.0 ns 2,3 SYSCLK rise and fall time 1.0 2.0 1.0 2.0 1.0 2.0 ns 4 4 SYSCLK duty cycle measured at 1.4 V 40 60 40 60 40 60 % 5 SYSCLK jitter — ±150 — ±150 — ±150 ps 5 6 Internal PLL relock time — 100 — 100 — 100 µs 6, 7 Notes: 1. Times shown in specifications are only valid for the range of processor core frequencies specified. 2. Caution: The SYSCLK frequency and PLL_CFG0–PLL_CFG3 settings must be chosen such that the resulting CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. 3. AC timing specifications are tested up to the maximum SYSCLK (bus) frequency shown in Table 5. However, it is theoretically possible to attain higher SYSCLK frequencies if allowed for by system design. 4. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V. 5. This number refers to cycle-to-cycle jitter. 6. PLL relock time is the maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the power-on reset sequence. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time (100 µs) during the power-on reset sequence. 7. Relock timing is guaranteed by design and is not tested. VM CVil CVih VM = Midpoint Voltage (1.4 V) SYSCLK 1 2 3 4 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com AR CH IVE D B Y F RE ES CA LE SE MI CO ND UC TO R, INC . |
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